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User's Manual
PD780058, 780058Y Subseries
8-Bit Single-Chip Microcontrollers
PD780053 PD780054 PD780055 PD780056 PD780058 PD780058B PD78F0058 PD780053(A) PD780054(A) PD780055(A) PD780056(A) PD780058B(A)
PD780053Y PD780054Y PD780055Y PD780056Y PD780058BY PD78F0058Y PD780053Y(A) PD780054Y(A) PD780055Y(A) PD780056Y(A) PD780058BY(A)
Document No. U12013EJ3V2UD00 (3rd edition) Date Published February 2003 N CP (K) 1997, 2003
Printed in Japan
[MEMO]
2
User's Manual U12013EJ3V2UD
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP, EEPROM, and IEBus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
User's Manual U12013EJ3V2UD
3
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
* The information in this document is current as of January, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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User's Manual U12013EJ3V2UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Europe) GmbH
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Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
User's Manual U12013EJ3V2UD
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Major Revisions in This Edition (1/2)
Page Throughout Deletion of following product * PD780058Y Addition of following products * PD780058B, 780058BY, 780053(A), 780053Y(A), 780054(A), 780054Y(A), 780055(A), 780055Y(A), 780056(A), 780056Y(A), 780058B(A), 780058BY(A) Deletion of following packages * 80-pin plastic QFP (GC-3B9 type) * 80-pin plastic TQFP (GK-BE9 type) Addition of following package * 80-pin plastic TQFP (GK-9EU type) pp. 31, 32, 38, 39 1.1 Features, 1.7 Outline of Functions * Change of operating voltage range of A/D and D/A converters of PD780058 and 78F0058 * Change of supply voltage of PD78F0058 Addition of 1.9 Differences Between Standard Model and (A) Model 2.1 Features, 2.7 Outline of Functions * Change of operating voltage range of A/D and D/A converters of PD78F0058Y * Change of supply voltage of PD78F0058Y Addition of 2.9 Differences Between Standard Model and (A) Model Change of processing when A/D converter is not used in 3.2.11 AVREF0 Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and VPP pins in Table 3-1 Pin I/O Circuit Types Change of processing when A/D converter is not used in 4.2.11 AVREF0 Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and VPP pins in Table 4-1 Pin I/O Circuit Types Modification of Note 2 in 6.2.8 Port 6 Addition of note on feedback resistor to Figure 7-3 Processor Clock Control Register Format Addition of Table 8-5 INTP1/TI01 Pin Valid Edge and CR00 Capture Trigger Valid Edge Addition of Table 8-6 INTP0/TI00 Pin Valid Edge and CR01 Capture Trigger Valid Edge Correction of note on valid edge of INTP0/TI00/P00 and INTP1/TI01/P01 pin in Figure 8-8 Format of External Interrupt Mode Register 0 Addition of Figure 8-17 Configuration of PPG Output Addition of Figure 8-18 PPG Output Operation Timing 8.5 16-Bit Addition of Addition of Addition of Addition of Addition of Addition of Addition of Timer/Event Counter Operating Cautions description on TI01/P01/INTP1 to (5) Valid edge setting (c) One-shot pulse output function to (6) Re-trigger of one-shot pulse (8) Conflict operation (9) Timer operation (10) Capture operation (11) Compare operation (12) Edge detection Description
p. 40 pp. 41, 42, 48, 49
p. 50 p. 60 pp. 62, 63
p. 75 pp. 77, 78
p. 132 p. 149 p. 167 p. 168 p. 177
p. 185
pp. 201 to 204
p. 235
Modification of note on changing count clock in Figure 10-2 Timer Clock Select Register 2 Format Modification of note on changing count clock in Figure 11-2 Timer Clock Select Register 2 Format Addition of note on rewriting TCL2 in Figure 13-2 Format of Timer Clock Select Register 2
p. 242
p. 252
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User's Manual U12013EJ3V2UD
Major Revisions in This Edition (2/2)
Page p. 263 Description Modification of Figure 14-5 A/D Converter Basic Operation Addition of Table 14-2 A/D Conversion Sampling Time and A/D Converter Start Delay Time Addition of 14.5 How to Read A/D Converter Characteristics Table 14.6 A/D Converter Cautions Change of description in (1) Power consumption in standby mode Addition of (3) Conflict operations Addition of (6) Input impedance of ANI0 to ANI7 pins Addition of (10) Timing at which A/D conversion result is undefined Addition of (11) Notes on board design Addition of (12) AVREF0 pin Addition of (13) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance p. 280 Addition of description of processing when D/A converter is not used in 15.5 D/A Converter Cautions (3) AVREF1 pin Addition of 17.4.7 Restrictions in I2C bus mode 2 Addition of 19.4.5 Restrictions in UART mode 2 Addition of Caution when interrupt is acknowledged to Figure 21-2 Interrupt Request Flag Register Format Addition of description on TI01/P01/INTP1 pin to Figure 21-5 Format of External Interrupt Mode Register 0 p. 525 p. 535 Addition of Caution to 25.1 ROM Correction Function Modification of Table 26-1 Differences Between PD78F0058, 78F0058Y and Mask ROM Versions Total revision of description on flash memory programming as 26.3 Flash Memory Characteristics pp. 567 to 596 pp. 597 to 626 pp. 627 to 657 Addition of CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION) Addition of CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION) Addition of CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V)) pp. 658, 659 pp. 660, 661 pp. 662 to 665 pp. 666, 667 Addition of CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES) Addition of CHAPTER 32 PACKAGE DRAWINGS Addition of CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS Correction of APPENDIX A DIFFERENCES BETWEEN PD78054, 78058F, AND 780058 SUBSERIES Total revision of APPENDIX B DEVELOPMENT TOOLS Transfer of description of embedded software to APPENDIX B DEVELOPMENT TOOLS
pp. 267, 268 pp. 269, 270, 272, 273
p. 379 p. 468 p. 477
p. 483
pp. 538 to 549
pp. 668 to 684
The mark
shows major revised points.
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PREFACE
Readers
This manual has been prepared for user engineers who wish to understand the functions of the PD780058 and 780058Y Subseries and design and develop its application systems and programs. This manual is intended for the products in the following subseries. * PD780058 Subseries
PD780053, 780054, 780055, 780056, 780058, 780058B, 78F0058, 780053(A),
780054(A), 780055(A), 780056(A), 780058B(A) * PD780058Y Subseries
PD780053Y, 780054Y, 780055Y, 780056Y, 780058BY, 78F0058Y, 780053Y(A),
780054Y(A), 780055Y(A), 780056Y(A), 780058BY(A) These products are collectively referred to as the "PD780058, 780058Y Subseries" in this manual. Purpose This manual is intended to give users an understanding of the functions described in the organization below. Organization The PD780058, 780058Y Subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 Series).
PD780058, 780058Y Subseries User's Manual (This manual)
Pin functions Internal block functions Interrupts Other on-chip peripheral functions Electrical specifications
78K/0 Series User's Manual Instructions CPU functions Instruction set Explanation of each instruction
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User's Manual U12013EJ3V2UD
How to Read This Manual
It is assumed that readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. When using this manual as the manual for the PD780053(A), 780054(A), 780055(A), 780056(A), 780058B(A), 780053Y(A), 780054Y(A), 780055Y(A), 780056Y(A), and 780058BY(A), The only difference between these products and the PD780053, 780054, 780055, 780056, 780058B, 780053Y, 780054Y, 780055Y, 780056Y, and 780058BY is the quality grade (see 1.9 Differences Between Standard Model and (A) Model, and 2.9 Differences Between Standard Model and (A) Model). The correspondence between the standard model and (A) model is as follows in CHAPTER 6 PORT FUNCTIONS to CHAPTER 27 INSTRUCTION SET OUTLINE.
PD780053 PD780053(A) PD780054 PD780054(A) PD780055 PD780055(A) PD780056 PD780056(A) PD780058B PD780058B(A)
PD780053Y PD780053Y(A) PD780054Y PD780054Y(A) PD780055Y PD780055Y(A) PD780056Y PD780056Y(A) PD780058BY PD780058BY(A)
To gain a general understanding the functions: Read this manual in the order of the contents. To know the PD780058 and 780058Y Subseries instruction functions in detail: Refer to the 78K/0 Series Instructions User's Manual (U12326E) How to interpret the register format: For a bit number enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and defined in the header file named sfrbit.h in the CC78K0. To learn the function of a register whose register name is known: Refer to APPENDIX C REGISTER INDEX. To see application examples of each function of the PD780058, 780058Y Subseries: Refer to 78K/0 Series Basics (III) Application Note (U10182E) separately available. To understand the electrical specifications of the PD780058, 780058Y Subseries: See CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION), CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION), CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V)). Caution Examples in this manual employ the "standard" quality grade for general electronics. When using examples in this manual for the "special" quality grade, review the quality grade of each part and/or circuit actually used.
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Chapter Organization: This manual divides the descriptions for the PD780058 and 780058Y Subseries into different chapters as shown below. Read only the chapters related to the device being used.
Chapter
PD780058 Subseries
-- -- --
PD780058Y Subseries
-- -- --
CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 CHAPTER 6 CHAPTER 7 CHAPTER 8 CHAPTER 9
Outline (PD780058 Subseries) Outline (PD780058Y Subseries) Pin Functions (PD780058 Subseries) Pin Functions (PD780058Y Subseries) CPU Architecture Port Functions Clock Generator 16-Bit Timer/Event Counter 8-Bit Timer/Event Counter
CHAPTER 10 Watch Timer CHAPTER 11 Watchdog Timer CHAPTER 12 Clock Output Controller CHAPTER 13 Buzzer Output Controller CHAPTER 14 A/D Converter CHAPTER 15 D/A Converter CHAPTER 16 Serial Interface Channel 0 (PD780058 Subseries) CHAPTER 17 Serial Interface Channel 0 (PD780058Y Subseries) CHAPTER 18 Serial Interface Channel 1 CHAPTER 19 Serial Interface Channel 2 CHAPTER 20 Real-Time Output Port CHAPTER 21 Interrupt and Test Functions CHAPTER 22 External Device Expansion Function CHAPTER 23 Standby Function CHAPTER 24 Reset Function CHAPTER 25 ROM Correction CHAPTER 26 PD78F0058, PD78F0058Y CHAPTER 27 Outline of Instruction Set CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION) CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION) CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V)) CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES) CHAPTER 32 PACKAGE DRAWINGS CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
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Differences Between PD780058 and PD780058Y Subseries: The PD780058 and PD780058Y Subseries differ in the following functions of serial interface channel 0.
Modes of serial interface channel 0
PD780058 Subseries
--
PD780058Y Subseries
--
3-wire serial I/O mode 2-wire serial I/O mode SBI (serial bus interface) mode I C (inter IC) bus mode : Supported --: Not supported
2
Legend
Data significance: Active low representations: Note: Caution: Remark: Numeral representations:
Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Footnote for item marked with Note in the text. Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No. This manual U12326E U10182E
PD780058, 780058Y Subseries User's Manual
78K/0 Series Instruction User's Manual 78K/0 Series Basics (III) Application Note
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
User's Manual U12013EJ3V2UD
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Documents Related to Software Development Tools (User's Manuals)
Document Name RA78K0 Assember Package Operation Language Structure Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (WindowsTM Based) External Part User Open Interface Specification ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based) Document No. U14445E U14446E U11789E U14297E U14298E U15373E U15802E U15185E U11537E U11536E U14610E
Documents Related to Hardware Development Tools (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780308-NS-EM1 Emulation Board IE-78001-R-A In-Circuit Emulator IE-780308-R-EM Emulation Board Document No. U13731E U14889E U13304E U14142E U11362E
Documents Related to Flash Memory Writing
Document Name PG-FP3 Flash Memory Programmer User's Manual PG-FP4 Flash Memory Programmer User's Manual Document No. U13502E U15260E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
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User's Manual U12013EJ3V2UD
CONTENTS
CHAPTER 1 OUTLINE (PD780058 SUBSERIES) ......................................................................... 1.1 Features ................................................................................................................................ 1.2 Applications ......................................................................................................................... 1.3 Ordering Information .......................................................................................................... 1.4 Pin Configuration (Top View) ............................................................................................. 1.5 78K/0 Series Lineup ............................................................................................................ 1.6 Block Diagram ..................................................................................................................... 1.7 Outline of Function ............................................................................................................. 1.8 Mask Options ....................................................................................................................... 1.9 Differences Between Standard Model and (A) Model .................................................... CHAPTER 2 OUTLINE (PD780058Y SUBSERIES) ....................................................................... 2.1 Features ................................................................................................................................ 2.2 Applications ......................................................................................................................... 2.3 Ordering Information .......................................................................................................... 2.4 Pin Configuration (Top View) ............................................................................................. 2.5 78K/0 Series Lineup ............................................................................................................ 2.6 Block Diagram ..................................................................................................................... 2.7 Outline of Functions ........................................................................................................... 2.8 Mask Options ....................................................................................................................... 2.9 Differences Between Standard Model and (A) Model .................................................... CHAPTER 3 PIN FUNCTIONS (PD780058 SUBSERIES) ............................................................. 3.1 Pin Function List ................................................................................................................. 3.2 Description of Pin Functions ............................................................................................
3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 P00 to P05, P07 (Port 0) ........................................................................................................ P10 to P17 (Port 1) ................................................................................................................. P20 to P27 (Port 2) ................................................................................................................. P30 to P37 (Port 3) ................................................................................................................. P40 to P47 (Port 4) ................................................................................................................. P50 to P57 (Port 5) ................................................................................................................. P60 to P67 (Port 6) ................................................................................................................. P70 to P72 (Port 7) ................................................................................................................. P120 to P127 (Port 12) ...........................................................................................................
31 31 32 32 33 35 37 38 40 40 41 41 42 42 43 45 47 48 50 50 51 51 55
55 55 56 57 57 58 58 59 59 60 60 60 60 60 60 60 60 61 61 61
3.2.10 P130 and P131 (Port 13) ........................................................................................................ 3.2.11 AVREF0 ...................................................................................................................................... 3.2.12 AVREF1 ...................................................................................................................................... 3.2.13 AVSS ......................................................................................................................................... 3.2.14 RESET ..................................................................................................................................... 3.2.15 X1 and X2 ................................................................................................................................ 3.2.16 XT1 and XT2 ........................................................................................................................... 3.2.17 VDD0, VDD1 ................................................................................................................................ 3.2.18 VSS0, VSS1 ................................................................................................................................. 3.2.19 VPP (Flash memory version only) ........................................................................................... 3.2.20 IC (Mask ROM version only) ..................................................................................................
3.3 I/O Circuits and Recommended Connection of Unused Pins.......................................
62
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CHAPTER 4 PIN FUNCTIONS (PD780058Y SUBSERIES) .......................................................... 4.1 Pin Function List ................................................................................................................. 4.2 Description of Pin Functions ............................................................................................
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 P00 to P05, P07 (Port 0) ........................................................................................................ P10 to P17 (Port 1) ................................................................................................................. P20 to P27 (Port 2) ................................................................................................................. P30 to P37 (Port 3) ................................................................................................................. P40 to P47 (Port 4) ................................................................................................................. P50 to P57 (Port 5) ................................................................................................................. P60 to P67 (Port 6) ................................................................................................................. P70 to P72 (Port 7) ................................................................................................................. P120 to P127 (Port 12) ...........................................................................................................
66 66 70
70 71 71 72 73 73 73 74 74 75 75 75 75 75 75 75 75 76 76 76
4.2.10 P130 and P131 (Port 13) ....................................................................................................... 4.2.11 AVREF0 ...................................................................................................................................... 4.2.12 AVREF1 ...................................................................................................................................... 4.2.13 AVSS ......................................................................................................................................... 4.2.14 RESET ..................................................................................................................................... 4.2.15 X1 and X2 ................................................................................................................................ 4.2.16 XT1 and XT2 ........................................................................................................................... 4.2.17 VDD0, VDD1 ................................................................................................................................ 4.2.18 VSS0, VSS1 ................................................................................................................................. 4.2.19 VPP (Flash memory version only) ........................................................................................... 4.2.20 IC (Mask ROM version only) ..................................................................................................
4.3 I/O Circuits and Recommended Connection of Unused Pins....................................... CHAPTER 5 CPU ARCHITECTURE ................................................................................................. 5.1 Memory Spaces ...................................................................................................................
5.1.1 Internal program memory space .............................................................................................. 5.1.2 Internal data memory space .................................................................................................... 5.1.3 Special Function Register (SFR) area .................................................................................... 5.1.4 External memory space ........................................................................................................... 5.1.5 Data memory addressing .........................................................................................................
77 81 81
87 89 89 89 89
5.2 Processor Registers ...........................................................................................................
5.2.1 Control registers ....................................................................................................................... 5.2.2 General registers ...................................................................................................................... 5.2.3 Special-Function Registers (SFRs) ......................................................................................... 5.3.1 Relative addressing .................................................................................................................. 5.3.2 Immediate addressing .............................................................................................................. 5.3.3 Table indirect addressing ......................................................................................................... 5.3.4 Register addressing ................................................................................................................. 5.4.1 Implied addressing ................................................................................................................... 5.4.2 Register addressing ................................................................................................................. 5.4.3 Direct addressing ..................................................................................................................... 5.4.4 Short direct addressing ............................................................................................................ 5.4.5 Special-Function Register (SFR) addressing .......................................................................... 5.4.6 Register indirect addressing .................................................................................................... 5.4.7 Based addressing .....................................................................................................................
96
96 99 100 104 105 106 107 108 109 110 111 113 114 115
5.3 Instruction Address Addressing ....................................................................................... 104
5.4 Operand Address Addressing ........................................................................................... 108
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5.4.8 Based indexed addressing ....................................................................................................... 5.4.9 Stack addressing ......................................................................................................................
116 116
CHAPTER 6 PORT FUNCTIONS ...................................................................................................... 117 6.1 Port Functions ..................................................................................................................... 117 6.2 Port Configuration .............................................................................................................. 122
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 Port 0 ....................................................................................................................................... Port 1 ....................................................................................................................................... Port 2 (PD780058 Subseries) .............................................................................................. Port 2 (PD780058Y Subseries) ............................................................................................ Port 3 ....................................................................................................................................... Port 4 ....................................................................................................................................... Port 5 ....................................................................................................................................... Port 6 ....................................................................................................................................... Port 7 ....................................................................................................................................... 122 124 125 127 129 130 131 132 134 136 137
6.2.10 Port 12 ..................................................................................................................................... 6.2.11 Port 13 .....................................................................................................................................
6.3 Port Function Control Registers ....................................................................................... 138 6.4 Port Operations ................................................................................................................... 144
6.4.1 Writing to I/O port ..................................................................................................................... 6.4.2 Reading from I/O port .............................................................................................................. 6.4.3 Operations on I/O port ............................................................................................................. 144 144 144
6.5 Selection of Mask Option ................................................................................................... 145 CHAPTER 7 CLOCK GENERATOR .................................................................................................. 7.1 Clock Generator Functions ................................................................................................ 7.2 Clock Generator Configuration ......................................................................................... 7.3 Clock Generator Control Registers .................................................................................. 7.4 System Clock Oscillator .....................................................................................................
7.4.1 Main system clock oscillator .................................................................................................... 7.4.2 Subsystem clock oscillator ....................................................................................................... 7.4.3 Example of resonator with bad connection ............................................................................. 7.4.4 Divider ....................................................................................................................................... 7.4.5 When not using subsystem clock ............................................................................................ 7.5.1 Main system clock operations .................................................................................................. 7.5.2 Subsystem clock operations .................................................................................................... 7.6.1 Time required for switchover between system clock and CPU clock ..................................... 7.6.2 System clock and CPU clock switching procedure .................................................................
146 146 146 148 152
152 153 154 155 155 157 158 159 161
7.5 Clock Generator Operations .............................................................................................. 156
7.6 Changing System Clock and CPU Clock Settings ......................................................... 159
CHAPTER 8 16-BIT TIMER/EVENT COUNTER ............................................................................... 8.1 16-Bit Timer/Event Counter Functions ............................................................................. 8.2 16-Bit Timer/Event Counter Configuration ...................................................................... 8.3 16-Bit Timer/Event Counter Control Registers ............................................................... 8.4 16-Bit Timer/Event Counter Operations ...........................................................................
8.4.1 Interval timer operations .......................................................................................................... 8.4.2 PWM output operations ............................................................................................................ 8.4.3 PPG output operations ............................................................................................................. 8.4.4 Pulse width measurement operations .....................................................................................
162 162 164 169 179
179 181 184 186
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8.4.5 External event counter operation ............................................................................................. 8.4.6 Square-wave output operation ................................................................................................. 8.4.7 One-shot pulse output operation .............................................................................................
193 195 197
8.5 16-Bit Timer/Event Counter Operating Cautions ............................................................ 201 CHAPTER 9 8-BIT TIMER/EVENT COUNTER ................................................................................. 205 9.1 8-Bit Timer/Event Counter Functions ............................................................................... 205
9.1.1 8-bit timer/event counter mode ................................................................................................ 9.1.2 16-bit timer/event counter mode .............................................................................................. 205 208
9.2 8-Bit Timer/Event Counter Configuration ........................................................................ 210 9.3 8-Bit Timer/Event Counter Control Registers .................................................................. 214 9.4 Operations of 8-Bit Timer/Event Counters 1 and 2 ........................................................ 219
9.4.1 8-bit timer/event counter mode ................................................................................................ 9.4.2 16-bit timer/event counter mode .............................................................................................. 219 225
9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2 ........................................................... 230 CHAPTER 10 WATCH TIMER ............................................................................................................ 10.1 Watch Timer Functions ..................................................................................................... 10.2 Watch Timer Configuration .............................................................................................. 10.3 Watch Timer Control Registers ........................................................................................ 10.4 Watch Timer Operations ...................................................................................................
10.4.1 Watch timer operation ............................................................................................................ 10.4.2 Interval timer operation ..........................................................................................................
232 232 233 233 237
237 237
CHAPTER 11 WATCHDOG TIMER ................................................................................................... 11.1 Watchdog Timer Functions .............................................................................................. 11.2 Watchdog Timer Configuration ........................................................................................ 11.3 Watchdog Timer Control Registers ................................................................................. 11.4 Watchdog Timer Operations ............................................................................................
11.4.1 Watchdog timer operation ...................................................................................................... 11.4.2 Interval timer operation ..........................................................................................................
238 238 240 241 244
244 245
CHAPTER 12 CLOCK OUTPUT CONTROLLER ............................................................................. 12.1 Clock Output Controller Functions ................................................................................ 12.2 Clock Output Controller Configuration .......................................................................... 12.3 Clock Output Function Control Registers ..................................................................... CHAPTER 13 BUZZER OUTPUT CONTROLLER ........................................................................... 13.1 Buzzer Output Controller Functions .............................................................................. 13.2 Buzzer Output Controller Configuration ........................................................................ 13.3 Buzzer Output Function Control Registers ................................................................... CHAPTER 14 14.1 A/D 14.2 A/D 14.3 A/D 14.4 A/D A/D CONVERTER ...................................................................................................... Converter Functions ................................................................................................. Converter Configuration ........................................................................................... Converter Control Registers .................................................................................... Converter Operations ................................................................................................
246 246 247 247 250 250 250 251 254 254 254 258 262
262 264 265
14.4.1 Basic operations of A/D converter ......................................................................................... 14.4.2 Input voltage and conversion results ..................................................................................... 14.4.3 A/D converter operating mode ...............................................................................................
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14.5 How to Read the A/D Converter Characteristics Table ................................................ 267 14.6 A/D Converter Cautions ................................................................................................... 269 CHAPTER 15 15.1 D/A 15.2 D/A 15.3 D/A 15.4 D/A 15.5 D/A D/A CONVERTER ...................................................................................................... Converter Functions ................................................................................................. Converter Configuration ........................................................................................... Converter Control Registers .................................................................................... Converter Operations ................................................................................................ Converter Cautions ................................................................................................... 275 275 276 278 279 280 281 282 284 288 295
295 296 301 327 332
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES) .............................. 16.1 Functions of Serial Interface Channel 0 ........................................................................ 16.2 Configuration of Serial Interface Channel 0 ................................................................. 16.3 Control Registers of Serial Interface Channel 0 ........................................................... 16.4 Operations of Serial Interface Channel 0 ......................................................................
16.4.1 Operation stop mode .............................................................................................................. 16.4.2 3-wire serial I/O mode operation ........................................................................................... 16.4.3 SBI mode operation ............................................................................................................... 16.4.4 2-wire serial I/O mode operation ........................................................................................... 16.4.5 SCK0/P27 pin output manipulation .......................................................................................
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (PD780058Y SUBSERIES) ........................... 17.1 Functions of Serial Interface Channel 0 ........................................................................ 17.2 Configuration of Serial Interface Channel 0 ................................................................. 17.3 Control Registers of Serial Interface Channel 0 ........................................................... 17.4 Operations of Serial Interface Channel 0 ......................................................................
17.4.1 Operation stop mode .............................................................................................................. 17.4.2 3-wire serial I/O mode operation ........................................................................................... 17.4.3 2-wire serial I/O mode operation ........................................................................................... 17.4.4 I 2C bus mode operation ......................................................................................................... 17.4.5 Cautions on use of I2C bus mode ......................................................................................... 17.4.6 Restrictions in I2C bus mode 1 .............................................................................................. 17.4.7 Restrictions in I2C bus mode 2 .............................................................................................. 17.4.8 SCK0/SCL/P27 pin output manipulation ...............................................................................
333 334 336 340 347
347 348 352 357 374 377 379 380
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 ........................................................................... 18.1 Functions of Serial Interface Channel 1 ........................................................................ 18.2 Configuration of Serial Interface Channel 1 ................................................................. 18.3 Control Registers of Serial Interface Channel 1 ........................................................... 18.4 Operations of Serial Interface Channel 1 ......................................................................
18.4.1 Operation stop mode .............................................................................................................. 18.4.2 3-wire serial I/O mode operation ........................................................................................... 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function .........................
382 382 383 386 394
394 395 398
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ........................................................................... 19.1 Functions of Serial Interface Channel 2 ........................................................................ 19.2 Configuration of Serial Interface Channel 2 ................................................................. 19.3 Control Registers of Serial Interface Channel 2 ........................................................... 19.4 Operation of Serial Interface Channel 2 ........................................................................
19.4.1 Operation stop mode ..............................................................................................................
427 427 428 432 442
442
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19.4.2 Asynchronous serial interface (UART) mode (with time-division transfer function) ............ 19.4.3 3-wire serial I/O mode ............................................................................................................ 19.4.4 Restrictions in UART mode 1 ................................................................................................ 19.4.5 Restrictions in UART mode 2 ................................................................................................
444 458 465 468
CHAPTER 20 REAL-TIME OUTPUT PORT ..................................................................................... 20.1 Real-Time Output Port Functions ................................................................................... 20.2 Real-Time Output Port Configuration ............................................................................ 20.3 Real-Time Output Port Control Registers ...................................................................... CHAPTER 21 INTERRUPT AND TEST FUNCTIONS ...................................................................... 21.1 Interrupt Function Types .................................................................................................. 21.2 Interrupt Sources and Configuration ............................................................................. 21.3 Interrupt Function Control Registers ............................................................................. 21.4 Interrupt Servicing Operations .......................................................................................
21.4.1 Non-maskable interrupt request acknowledgment operation ............................................... 21.4.2 Maskable interrupt request acknowledgment operation ....................................................... 21.4.3 Software interrupt request acknowledgment operation ........................................................ 21.4.4 Multiple interrupt servicing ..................................................................................................... 21.4.5 Interrupt request pending ....................................................................................................... 21.5.1 Registers controlling test function ......................................................................................... 21.5.2 Test input signal acknowledgment operation ........................................................................
469 469 470 472 474 474 475 479 488
488 491 494 494 497 498 500
21.5 Test Function ..................................................................................................................... 498
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ....................................................... 22.1 External Device Expansion Function ............................................................................. 22.2 External Device Expansion Function Control Register ............................................... 22.3 External Device Expansion Function Timing ................................................................ 22.4 Example of Connection with Memory ............................................................................
501 501 505 507 512
CHAPTER 23 STANDBY FUNCTION .............................................................................................. 513 23.1 Standby Function and Configuration ............................................................................. 513
23.1.1 Standby function ..................................................................................................................... 23.1.2 Standby function control register ........................................................................................... 23.2.1 HALT mode ............................................................................................................................. 23.2.2 STOP mode ............................................................................................................................ 513 514 515 518
23.2 Standby Function Operations ......................................................................................... 515
CHAPTER 24 RESET FUNCTION .................................................................................................... 521 24.1 Reset Function .................................................................................................................. 521 CHAPTER 25 ROM CORRECTION ................................................................................................. 25.1 ROM Correction Function ................................................................................................ 25.2 ROM Correction Configuration ....................................................................................... 25.3 ROM Correction Control Registers ................................................................................. 25.4 ROM Correction Application............................................................................................ 25.5 ROM Correction Usage Example .................................................................................... 25.6 Program Execution Flow .................................................................................................. 25.7 ROM Correction Cautions ................................................................................................ 525 525 525 527 528 531 532 534
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CHAPTER 26 PD78F0058, 78F0058Y ............................................................................................ 26.1 Internal memory Size Switching Register ..................................................................... 26.2 Internal Expansion RAM Size Switching Register ....................................................... 26.3 Flash Memory Characteristics ........................................................................................
26.3.1 Programming environment ..................................................................................................... 26.3.2 Communication mode ............................................................................................................ 26.3.3 On-board pin processing ........................................................................................................ 26.3.4 Connection of adapter for flash writing .................................................................................
535 536 537 538
538 539 543 546
CHAPTER 27 INSTRUCTION SET OVERVIEW ............................................................................... 552 27.1 Conventions Used in Operation List .............................................................................. 553
27.1.1 Operand identifiers and description methods ....................................................................... 27.1.2 Description of operation column ............................................................................................ 27.1.3 Description of flag operation column ..................................................................................... 553 554 554
27.2 Operation List .................................................................................................................... 555 27.3 Instructions Listed by Addressing Type ........................................................................ 563 CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION) .................................... 567 CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION) ........................... 597 CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.5 V)) .... 627 CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES) .................................... 658 CHAPTER 32 PACKAGE DRAWINGS ............................................................................................. 660 CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS ..................................................... 662 APPENDIX A DIFFERENCES BETWEEN PD78054, 78058F, AND 780058 SUBSERIES ......... 666 APPENDIX B DEVELOPMENT TOOLS ........................................................................................... B.1 Software Package ............................................................................................................. B.2 Language Processing Software ...................................................................................... B.3 Control Software ............................................................................................................... B.4 Flash Memory Writing Tools ............................................................................................ B.5 Debugging Tools (Hardware) ...........................................................................................
B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A .................................................. B.5.2 When using in-circuit emulator IE-78001-R-A .......................................................................
668 670 670 671 671 672
672 673
B.6 B.7 B.8
Debugging Tools (Software) ............................................................................................ Embedded Software ......................................................................................................... System-Upgrade Method from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ................................................................................................................. B.9 Drawing and Footprint for Conversion Socket (EV-9200GC-80) ................................ B.10 Drawing of Conversion Adapter (TGK-080SDW, TGC-080SBP) .................................. B.11 Cautions on Designing Target System ..........................................................................
674 675 676 677 679 681
APPENDIX C REGISTER INDEX ..................................................................................................... 685 C.1 Register Index (Register Name) ....................................................................................... 685 C.2 Register Index (Symbol) .................................................................................................... 688 APPENDIX D REVISION HISTORY ................................................................................................. 691
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LIST OF FIGURES (1/8)
Figure No. 3-1 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21
Title
Page
Pin I/O Circuit List .................................................................................................................................... 64 Pin I/O Circuit List .................................................................................................................................... 79 Memory Map (PD780053, 780053(A), 780053Y, 780053Y(A)) ........................................................... 81 Memory Map (PD780054, 780054(A), 780054Y, 780054Y(A)) ........................................................... 82 Memory Map (PD780055, 780055(A), 780055Y, 780055Y(A)) ........................................................... 83 Memory Map (PD780056, 780056(A), 780056Y, 780056Y(A)) ........................................................... 84 Memory Map (PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A)) ................................... 85 Memory Map (PD78F0058, 78F0058Y) ................................................................................................ 86 Data Memory Addressing (PD780053, 780053(A), 780053Y, 780053Y(A)) ....................................... 90 Data Memory Addressing (PD780054, 780054(A), 780054Y, 780054Y(A)) ....................................... 91 Data Memory Addressing (PD780055, 780055(A), 780055Y, 780055Y(A)) ....................................... 92 Data Memory Addressing (PD780056, 780056(A), 780056Y, 780056Y(A)) ....................................... 93 Data Memory Addressing (PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A)) ............... 94 Data Memory Addressing (PD78F0058, 78F0058Y) ........................................................................... 95 Program Counter Format ......................................................................................................................... 96 Program Status Word Format .................................................................................................................. 96 Stack Pointer Format ............................................................................................................................... 98 Data to Be Saved to Stack Memory ........................................................................................................ 98 Data to Be Reset from Stack Memory .................................................................................................... 98 General-purpose Register Configuration ................................................................................................ 99 Port Types ............................................................................................................................................... 117 Block Diagram of P00 and P07 ............................................................................................................. 123 Block Diagram of P01 to P05 ................................................................................................................ 123 Block Diagram of P10 to P17 ................................................................................................................ 124 Block Diagram of P20, P21, and P23 to P26 ....................................................................................... 125 Block Diagram of P22 and P27 ............................................................................................................. 126 Block Diagram of P20, P21, and P23 to P26 ....................................................................................... 127 Block Diagram of P22 and P27 ............................................................................................................. 128 Block Diagram of P30 to P37 ................................................................................................................ 129 Block Diagram of P40 to P47 ................................................................................................................ 130 Block Diagram of Falling Edge Detector ............................................................................................... 130 Block Diagram of P50 to P57 ................................................................................................................ 131 Block Diagram of P60 to P63 ................................................................................................................ 133 Block Diagram of P64 to P67 ................................................................................................................ 133 Block Diagram of P70 ............................................................................................................................ 134 Block Diagram of P71 and P72 ............................................................................................................. 135 Block Diagram of P120 to P127 ............................................................................................................ 136 Block Diagram of P130 and P131 ......................................................................................................... 137 Port Mode Register Format ................................................................................................................... 140 Format of Pull-up Resistor Option Register .......................................................................................... 141 Format of Memory Expansion Mode Register ...................................................................................... 142
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LIST OF FIGURES (2/8)
Figure No. 6-22 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26
Title
Page
Format of Key Return Mode Register ................................................................................................... 143 Clock Generator Block Diagram ............................................................................................................ 147 Subsystem Clock Feedback Resistor ................................................................................................... 148 Format of Processor Clock Control Register ........................................................................................ 149 Format of Oscillation Mode Selection Register .................................................................................... 151 Main System Clock Waveform due to Writing to OSMS ...................................................................... 151 External Circuit of Main System Clock Oscillator ................................................................................. 152 External Circuit of Subsystem Clock Oscillator .................................................................................... 153 Examples of Resonator with Bad Connection ...................................................................................... 154 Main System Clock Stop Function ........................................................................................................ 157 Switching Between System Clock and CPU Clock .............................................................................. 161 Block Diagram of 16-Bit Timer/Event Counter ...................................................................................... 165 Block Diagram of 16-Bit Timer/Event Counter Output Controller ........................................................ 166 Format of Timer Clock Select Register 0 .............................................................................................. 170 Format of 16-Bit Timer Mode Control Register .................................................................................... 172 Format of Capture/Compare Control Register 0 .................................................................................. 173 Format of 16-Bit Timer Output Control Register .................................................................................. 175 Format of Port Mode Register 3 ............................................................................................................ 176 Format of External Interrupt Mode Register 0 ...................................................................................... 177 Format of Sampling Clock Select Register ........................................................................................... 178 Control Register Settings for Interval Timer Operation ........................................................................ 179 Interval Timer Configuration Diagram ................................................................................................... 180 Interval Timer Operation Timings .......................................................................................................... 180 Control Register Settings for PWM Output Operation ......................................................................... 182 Example of D/A Converter Configuration with PWM Output ............................................................... 183 TV Tuner Application Circuit Example ................................................................................................... 183 Control Register Settings for PPG Output Operation ........................................................................... 184 Configuration of PPG Output ................................................................................................................. 185 PPG Output Operation Timing ............................................................................................................... 185 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register .................................................................................................................... 186 Configuration Diagram for Pulse Width Measurement by Free-Running Counter .............................. 187 Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) ..................................................................... 187 Control Register Settings for Two Pulse Width Measurements with Free-Running Counter .............. 188 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) .................................................................................................................. 189 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers ................................................................................................................... 190 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) ................................................................... 191 Control Register Settings for Pulse Width Measurement by Means of Restart .................................. 192
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LIST OF FIGURES (3/8)
Figure No. 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 8-36 8-37 8-38 8-39 8-40 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 10-1 10-2 10-3 11-1 11-2 11-3 12-1 12-2 12-3
Title Timing of Pulse Width Measurement Operation by Means of Restart
Page
(with Rising Edge Specified) ................................................................................................................. 192 Control Register Settings in External Event Counter Mode ................................................................ 193 External Event Counter Configuration Diagram ................................................................................... 194 External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 194 Control Register Settings in Square-Wave Output Mode .................................................................... 195 Square-Wave Output Operation Timing ................................................................................................ 196 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger .................. 197 One-Shot Pulse Output Operation Timing Using Software Trigger ..................................................... 198 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger .................. 199 One-Shot Pulse Output Operation Timing Using External Trigger (with Rising Edge Specified) ...... 200 16-Bit Timer Register Start Timing ........................................................................................................ 201 Timing After Change of Compare Register During Timer Count Operation ....................................... 201 Capture Register Data Retention Timing .............................................................................................. 202 Operation Timing of OVF0 Flag ............................................................................................................ 203 Block Diagram of 8-Bit Timer/Event Counter ........................................................................................ 211 Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ....................................................... 212 Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ....................................................... 212 Format of Timer Clock Select Register 1 .............................................................................................. 215 Format of 8-Bit Timer Mode Control Register 1 ................................................................................... 216 Format of 8-Bit Timer Output Control Register ..................................................................................... 217 Format of Port Mode Register 3 ............................................................................................................ 218 Interval Timer Operation Timing ............................................................................................................ 219 External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 222 Square-Wave Output Operation Timing ................................................................................................ 224 Interval Timer Operation Timing ............................................................................................................ 225 External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 227 Square-Wave Output Operation Timing ................................................................................................ 229 Start Timing of 8-Bit Timer Registers 1 and 2 ...................................................................................... 230 External Event Counter Operation Timing ............................................................................................ 230 Timing After Compare Register Change During Timer Count Operation ............................................ 231 Watch Timer Block Diagram .................................................................................................................. 234 Format of Timer Clock Select Register 2 .............................................................................................. 235 Format of Watch Timer Mode Control Register .................................................................................... 236 Watchdog Timer Block Diagram ............................................................................................................ 240 Format of Timer Clock Select Register 2 .............................................................................................. 242 Format of Watchdog Timer Mode Register ........................................................................................... 243 Remote Controlled Output Application Example .................................................................................. 246 Clock Output Controller Block Diagram ................................................................................................ 247 Format of Timer Clock Select Register 0 .............................................................................................. 248
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Figure No. 12-4 13-1 13-2 13-3 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 15-1 15-2 15-3 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15
Title
Page
Format of Port Mode Register 3 ............................................................................................................ 249 Buzzer Output Controller Block Diagram .............................................................................................. 250 Format of Timer Clock Select Register 2 .............................................................................................. 252 Format of Port Mode Register 3 ............................................................................................................ 253 A/D Converter Block Diagram ............................................................................................................... 255 Format of A/D Converter Mode Register .............................................................................................. 259 Format of A/D Converter Input Select Register .................................................................................... 260 Format of External Interrupt Mode Register 1 ...................................................................................... 261 A/D Converter Basic Operation ............................................................................................................. 263 Relationship Between Analog Input Voltage and A/D Conversion Result ........................................... 264 A/D Conversion by Hardware Start ....................................................................................................... 265 A/D Conversion by Software Start ........................................................................................................ 266 Overall Error ........................................................................................................................................... 267 Quantization Error .................................................................................................................................. 267 Example of Method of Reducing Current Consumption in Standby Mode ......................................... 269 Analog Input Pin Handling ..................................................................................................................... 270 A/D Conversion End Interrupt Request Generation Timing ................................................................. 271 Timing of Reading Conversion Result (When Conversion Result is Undefined) ................................ 272 Timing of Reading Conversion Result (When Conversion Result is Normal) ..................................... 272 Example of Connecting Capacitor to AVREF0 Pin .................................................................................. 273 Internal Equivalent Circuit of Pins ANI0 to ANI7 .................................................................................. 274 Example of Connection If Signal Source Impedance Is High .............................................................. 274 D/A Converter Block Diagram ............................................................................................................... 276 Format of D/A Converter Mode Register .............................................................................................. 278 Use Example of Buffer Amplifier ........................................................................................................... 280 Serial Bus Interface (SBI) System Configuration Example .................................................................. 283 Block Diagram of Serial Interface Channel 0 ....................................................................................... 285 Format of Timer Clock Select Register 3 .............................................................................................. 289 Format of Serial Operating Mode Register 0 ....................................................................................... 290 Format of Serial Bus Interface Control Register .................................................................................. 292 Format of Interrupt Timing Specification Register ................................................................................ 294 3-Wire Serial I/O Mode Timing .............................................................................................................. 299 RELT and CMDT Operations ................................................................................................................. 299 Circuit for Switching Transfer Bit Order ................................................................................................. 300 Example of Serial Bus Configuration with SBI ..................................................................................... 301 SBI Transfer Timing ................................................................................................................................ 303 Bus Release Signal ............................................................................................................................... 304 Command Signal .................................................................................................................................... 304 Addresses ............................................................................................................................................... 305 Slave Selection by Address ................................................................................................................... 305
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LIST OF FIGURES (5/8)
Figure No. 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26 16-27 16-28 16-29 16-30 16-31 16-32 16-33 16-34 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 17-21 17-22 17-23 17-24
Title
Page
Commands ............................................................................................................................................. 306 Data ........................................................................................................................................................ 306 Acknowledge Signal ............................................................................................................................... 307 BUSY and READY Signals .................................................................................................................... 308 RELT, CMDT, RELD, and CMDD Operations (Master) ......................................................................... 313 RELD and CMDD Operations (Slave) ................................................................................................... 313 ACKT Operation ..................................................................................................................................... 314 ACKE Operations ................................................................................................................................... 315 ACKD Operations ................................................................................................................................... 316 BSYE Operation ..................................................................................................................................... 316 Pin Configuration ................................................................................................................................... 319 Address Transmission from Master Device to Slave Device (WUP = 1) ............................................. 321 Command Transmission from Master Device to Slave Device ............................................................ 322 Data Transmission from Master Device to Slave Device ..................................................................... 323 Data Transmission from Slave Device to Master Device ..................................................................... 324 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ...................................................... 327 2-Wire Serial I/O Mode Timing .............................................................................................................. 330 RELT and CMDT Operations ................................................................................................................. 331 SCK0/P27 Pin Configuration ................................................................................................................. 332 Serial Bus Configuration Example Using I2C Bus ................................................................................ 335 Block Diagram of Serial Interface Channel 0 ....................................................................................... 337 Format of Timer Clock Select Register 3 .............................................................................................. 341 Format of Serial Operating Mode Register 0 ....................................................................................... 342 Format of Serial Bus Interface Control Register .................................................................................. 343 Format of Interrupt Timing Specification Register ................................................................................ 345 3-Wire Serial I/O Mode Timing .............................................................................................................. 350 RELT and CMDT Operations ................................................................................................................. 350 Circuit for Switching Transfer Bit Order ................................................................................................. 351 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ...................................................... 352 2-Wire Serial I/O Mode Timing .............................................................................................................. 355 RELT and CMDT Operations ................................................................................................................. 356 Example of Serial Bus Configuration Using I2C Bus ......................................................................... I2C Bus Serial Data Transfer Timing ................................................................................................... Start Condition .................................................................................................................................... Address ............................................................................................................................................... Transfer Direction Specification .......................................................................................................... Acknowledge Signal ............................................................................................................................ Stop Condition ..................................................................................................................................... Wait Signal .......................................................................................................................................... Pin Configuration ................................................................................................................................ Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) ............ Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) ............ Start Condition Output ........................................................................................................................ 357 358 359 359 359 360 360 361 366 368 371 374
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LIST OF FIGURES (6/8)
Figure No. 17-25 17-26 17-27 17-28 17-29 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 18-24
Title
Page 375 376 380 380 381
Slave Wait Release (Transmission) .................................................................................................... Slave Wait Release (Reception) ......................................................................................................... SCK0/SCL/P27 Pin Configuration ...................................................................................................... SCK0/SCL/P27 Pin Configuration ...................................................................................................... Logic Circuit of SCL Signal ................................................................................................................
Block Diagram of Serial Interface Channel 1 ....................................................................................... 384 Format of Timer Clock Select Register 3 .............................................................................................. 387 Format of Serial Operation Mode Register 1 ....................................................................................... 388 Format of Automatic Data Transmit/Receive Control Register ............................................................ 389 Format of Automatic Data Transmit/Receive Interval Specification Register ...................................... 390 3-Wire Serial I/O Mode Timing .............................................................................................................. 396 Circuit for Switching Transfer Bit Order ................................................................................................. 397 Basic Transmission/Reception Mode Operation Timing ....................................................................... 406 Basic Transmission/Reception Mode Flowchart ................................................................................... 407 Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) ......................................................................................................... 408 Basic Transmission Mode Operation Timing ......................................................................................... 410 Basic Transmission Mode Flowchart ..................................................................................................... 411 Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ............................. 412 Repeat Transmission Mode Operation Timing ...................................................................................... 414 Repeat Transmission Mode Flowchart .................................................................................................. 415 Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) ........................... 416 Automatic Transmission/Reception Suspension and Restart .............................................................. 418 System Configuration When Busy Control Option Is Used .................................................................. 419 Operation Timing When Busy Control Option Is Used (When BUSY0 = 0) ........................................ 420 Busy Signal and Wait Release (When BUSY0 = 0) ............................................................................. 421 Operation Timing When Busy & Strobe Control Options Are Used (When BUSY0 = 0) .................... 422 Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSY0 = 1) ...................... 423 Automatic Data Transmit/Receive Interval Time ................................................................................... 424 Operation Timing with Automatic Data Transmit/Receive Function Performed Using Internal Clock ......................................................................................................................................... 425
19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11
Block Diagram of Serial Interface Channel 2 ....................................................................................... 429 Baud Rate Generator Block Diagram ................................................................................................... 430 Format of Serial Operating Mode Register 2 ....................................................................................... 432 Format of Asynchronous Serial Interface Mode Register .................................................................... 433 Format of Asynchronous Serial Interface Status Register ................................................................... 436 Format of Baud Rate Generator Control Register ................................................................................ 437 Format of Serial Interface Pin Select Register ..................................................................................... 441 Format of Asynchronous Serial Interface Transmit/Receive Data ....................................................... 452 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing ....... 454 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing ........... 455 Receive Error Timing ............................................................................................................................. 456
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LIST OF FIGURES (7/8)
Figure No. 19-12 19-13 19-14 19-15 19-16 19-17 20-1 20-2 20-3 20-4 20-5 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 21-17 21-18 21-19 21-20 21-21 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8
Title Status of Receive Buffer Register (RXB) and Generation of Interrupt Request (INTSR)
Page
When Reception Is Stopped .................................................................................................................. 457 3-Wire Serial I/O Mode Timing .............................................................................................................. 463 Circuit for Switching Transfer Bit Order ................................................................................................. 464 Reception Completion Interrupt Request Generation Timing (When ISRM = 1) ................................ 465 Receive Buffer Register Read Disable Period ...................................................................................... 466 P23 Output Selector .............................................................................................................................. 468 Real-Time Output Port Block Diagram .................................................................................................. 470 Real-Time Output Buffer Register Configuration .................................................................................. 471 Format of Port Mode Register 12 .......................................................................................................... 472 Format of Real-Time Output Port Mode Register ................................................................................ 472 Format of Real-Time Output Port Control Register .............................................................................. 473 Basic Configuration of Interrupt Function ............................................................................................. 477 Format of Interrupt Request Flag Register ........................................................................................... 480 Interrupt Mask Flag Register Format .................................................................................................... 481 Format of Priority Specification Flag Register ...................................................................................... 482 Format of External Interrupt Mode Register 0 ...................................................................................... 483 Format of External Interrupt Mode Register 1 ...................................................................................... 484 Format of Sampling Clock Select Register ........................................................................................... 485 Noise Eliminator I/O Timing (During Rising Edge Detection) .............................................................. 486 Format of Program Status Word ........................................................................................................... 487 Non-Maskable Interrupt Request Occurrence and Acknowledgment Flowchart ................................ 489 Non-Maskable Interrupt Request Acknowledgment Timing ................................................................. 489 Non-Maskable Interrupt Request Acknowledgment Operation ............................................................ 490 Interrupt Request Acknowledgment Processing Algorithm .................................................................. 492 Interrupt Request Acknowledgment Timing (Minimum Time) .............................................................. 493 Interrupt Request Acknowledgment Timing (Maximum Time) ............................................................. 493 Multiple Interrupt Servicing Example .................................................................................................... 495 Interrupt Request Pending Timing ......................................................................................................... 497 Basic Configuration of Test Function .................................................................................................... 498 Format of Interrupt Request Flag Register 1L ...................................................................................... 499 Format of Interrupt Mask Flag Register 1L .......................................................................................... 499 Format of Key Return Mode Register ................................................................................................... 500 Memory Map When Using External Device Expansion Function ........................................................ 502 Format of Memory Expansion Mode Register ...................................................................................... 505 Format of Internal Memory Size Switching Register ............................................................................ 506 Instruction Fetch from External Memory ............................................................................................... 508 External Memory Read Timing .............................................................................................................. 509 External Memory Write Timing .............................................................................................................. 510 External Memory Read Modify Write Timing ........................................................................................ 511 Example of Connection Between PD780054 and Memory ................................................................ 512
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LIST OF FIGURES (8/8)
Figure No. 23-1 23-2 23-3 23-4 23-5 24-1 24-2 24-3 24-4 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 26-1 26-2 23-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9
Title
Page
Format of Oscillation Stabilizat Time Selection Register ..................................................................... 514 HALT Mode Release by Interrupt Request Generation ........................................................................ 516 HALT Mode Release by RESET Input .................................................................................................. 517 STOP Mode Release by Interrupt Request Generation ....................................................................... 519 STOP Mode Release by RESET Input ................................................................................................. 520 Reset Function Block Diagram .............................................................................................................. 521 Reset Timing by RESET Input .............................................................................................................. 522 Reset Timing due to Watchdog Timer Overflow ................................................................................... 522 Reset Timing by RESET Input in STOP Mode ..................................................................................... 522 ROM Correction Block Diagram ............................................................................................................ 525 Format of Correction Address Registers 0 and 1 ................................................................................. 526 Format of Correction Control Register .................................................................................................. 527 Example of Storing to EEPROM (When One Place Is Corrected) ...................................................... 528 Initialization Routine ............................................................................................................................... 529 ROM Correction Operation .................................................................................................................... 530 ROM Correction Usage Example .......................................................................................................... 531 Program Transition Diagram (When One Place Is Corrected) ............................................................. 532 Program Transition Diagram (When Two Places Are Corrected) ......................................................... 533 Format of Memory Size Switching Register ......................................................................................... 536 Format of Internal Expansion RAM Size Switching Register .............................................................. 537 Environment for Writing Program to Flash Memory ............................................................................. 538 Communication Mode Selection Format ............................................................................................... 539 Example of Connection with Dedicated Flash Programmer ................................................................ 540 VPP Pin Connection Example ................................................................................................................ 543 Signal Conflict (Input Pin of Serial Interface) ....................................................................................... 544 Abnormal Operation of Other Device .................................................................................................... 544 Signal Conflict (RESET Pin) .................................................................................................................. 545 Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-0) .............................. 546 Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-1) .............................. 547 Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-2) .............................. 548 Wiring Example for Flash Writing Adapter in UART Mode (UART ch-0) ............................................. 549 Wiring Example for Flash Writing Adapter in UART Mode (UART ch-1) ............................................. 550 Wiring Example for Flash Writing Adapter in Pseudo 3-Wire Mode.................................................... 551 Configuration of Development Tools ..................................................................................................... 669 EV-9200GC-80 Drawing (For Reference Only) ..................................................................................... 677 EV-9200GC-80 Footprint (For Reference Only) ................................................................................... 678 TGK-080SDW Drawing (For Reference Only) (Unit: mm) .................................................................... 679 TGC-080SBP Drawing (For Reference Only) (Unit: mm) ................................................................... 680 Distance Between In-Circuit Emulator and Conversion Socket (80GC) .............................................. 681 Connection Condition of Target System (NP-80GC-TQ) ...................................................................... 682 Distance Between In-Circuit Emulator and Conversion Socket (80GK) .............................................. 683 Connection Condition of Target System (NP-80GK) ............................................................................ 684
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LIST OF TABLES (1/3)
Table No. 1-1 1-2 2-1 2-2 3-1 4-1 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8
Title
Page
Mask Options of Mask ROM Versions .................................................................................................... 40 Differences Between Standard Model and (A) Model ............................................................................ 40 Mask Options of Mask ROM Versions .................................................................................................... 50 Differences Between Standard Model and (A) Model ............................................................................ 50 Pin I/O Circuit Types ................................................................................................................................ 62 Pin I/O Circuit Types ................................................................................................................................ 77 Vector ........................................................................................................................................................ 88 Special-Function Register List .............................................................................................................. 101 Port Functions (PD780058 Subseries) ............................................................................................... 118 Port Functions (PD780058Y Subseries) ............................................................................................. 120 Port Configuration .................................................................................................................................. 122 Pull-up Resistor of Port 6 ...................................................................................................................... 132 Port Mode Register and Output Latch Settings When Using Alternate Functions ............................. 139 Comparison Between Mask ROM Version and Flash Memory Version .............................................. 145 Clock Generator Configuration .............................................................................................................. 146 Relationship Between CPU Clock and Minimum Instruction Execution Time ..................................... 150 Maximum Time Required for CPU Clock Switchover ........................................................................... 160 16-Bit Timer/Event Counter Interval Times ........................................................................................... 162 16-Bit Timer/Event Counter Square-Wave Output Ranges .................................................................. 163 16-Bit Timer/Event Counter Configuration ............................................................................................ 164 INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge ..................................................... 167 INTP1/TI01 Pin Valid Edge and CR00 Capture Trigger Valid Edge ..................................................... 167 INTP0/TI00 Pin Valid Edge and CR01 Capture Trigger Valid Edge ..................................................... 168 16-Bit Timer/Event Counter Interval Times ........................................................................................... 181 16-Bit Timer/Event Counter Square-Wave Output Ranges .................................................................. 196 Interval Times of 8-Bit Timer/Event Counters 1 and 2 ......................................................................... 206 Square-Wave Output Ranges of 8-Bit Timer/Event Counters 1 and 2 ................................................ 207 Interval Times When 8-Bit Timer/Event Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter ................................................................................................................... 208 Square-Wave Output Ranges When 8-Bit Timer/Event Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter ............................................................................................. 209 8-Bit Timer/Event Counter Configuration .............................................................................................. 210 Interval Time of 8-Bit Timer/Event Counter 1 ....................................................................................... 220 Interval Time of 8-Bit Timer/Event Counter 2 ....................................................................................... 221 Square-Wave Output Ranges of 8-Bit Timer/Event Counters 1 and 2 ................................................ 223
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Table No. 9-9 9-10
Title Interval Times When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2)
Page
Are Used as 16-Bit Timer/Event Counter ............................................................................................. 226 Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter ............................................................................................. 228 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 12-1 13-1 14-1 14-2 14-3 15-1 16-1 16-2 16-3 17-1 17-2 17-3 17-4 18-1 18-2 18-3 19-1 19-2 19-3 19-4 19-5 19-6 Interval Timer Interval Time ................................................................................................................... 232 Watch Timer Configuration .................................................................................................................... 233 Interval Timer Interval Time ................................................................................................................... 237 Watchdog Timer Program Loop Detection Times ................................................................................. 238 Interval Times ......................................................................................................................................... 239 Watchdog Timer Configuration .............................................................................................................. 240 Watchdog Timer Program Loop Detection Time ................................................................................... 244 Interval Timer Interval Time ................................................................................................................... 245 Clock Output Controller Configuration .................................................................................................. 247 Buzzer Output Controller Configuration ................................................................................................ 250 A/D Converter Configuration ................................................................................................................. 254 A/D Converter Sampling Time and A/D Conversion Start Delay Time ................................................ 263 Resistances and Capacitances of Equivalent Circuit (Reference Values) .......................................... 274 D/A Converter Configuration ................................................................................................................. 276 Differences Between Channels 0, 1, and 2 .......................................................................................... 281 Configuration of Serial Interface Channel 0 ......................................................................................... 284 Various Signals in SBI Mode ................................................................................................................. 317 Differences Between Channels 0, 1, and 2 .......................................................................................... 333 Configuration of Serial Interface Channel 0 ......................................................................................... 336 Interrupt Request Signal Generation of Serial Interface Channel 0 .................................................... 339 Signals in I2C Bus Mode ..................................................................................................................... 365
Configuration of Serial Interface Channel 1 ......................................................................................... 383 Interval Timing According to CPU Processing (When Internal Clock Is Operating) ........................... 425 Interval Time According to CPU Processing (with External Clock) ..................................................... 426 Configuration of Serial Interface Channel 2 ......................................................................................... 428 Operating Mode Settings of Serial Interface Channel 2 ...................................................................... 434 Relationship Between Main System Clock and Baud Rate ................................................................. 439 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H) ..... 440 Relationship Between Main System Clock and Baud Rate ................................................................. 449 Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H) ..... 450
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LIST OF TABLES (3/3)
Table No. 19-7 20-1 20-2 20-3 21-1 21-2 21-3 21-4 21-5 21-6 22-1 22-2 22-3 23-1 23-2 23-3 23-4 24-1 25-1 26-1 26-2 26-3 26-4 26-5 27-1 33-1 A-1 B-1
Title
Page
Receive Error Causes ............................................................................................................................ 456 Real-Time Output Port Configuration .................................................................................................... 470 Operation in Real-Time Output Buffer Register Manipulation ............................................................. 471 Real-Time Output Port Operating Mode and Output Trigger ............................................................... 473 Interrupt Source List .............................................................................................................................. 475 Various Flags Corresponding to Interrupt Request Sources ............................................................... 479 Times from Maskable Interrupt Request Generation to Interrupt Servicing ....................................... 491 Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing ...................... 494 Test Input Sources ................................................................................................................................. 498 Flags Corresponding to Test Input Signals ........................................................................................... 498 Pin Functions in External Memory Expansion Mode ........................................................................... 501 State of Port 4 to 6 Pins in External Memory Expansion Mode .......................................................... 501 Values After Internal Memory Size Switching Register Is Reset ......................................................... 506 HALT Mode Operating Status ................................................................................................................ 515 Operation After HALT Mode Release .................................................................................................... 517 STOP Mode Operating Status ............................................................................................................... 518 Operation After STOP Mode Release ................................................................................................... 520 Hardware Status After Reset ................................................................................................................. 523 ROM Correction Configuration .............................................................................................................. 525 Differences Between PD78F0058, 78F0058Y and Mask ROM Versions .......................................... 535 Internal Memory Size Switching Register Setting Values .................................................................... 536 Internal Expansion RAM Size Switching Register Setting Values ....................................................... 537 Communication Mode List ..................................................................................................................... 539 Pin Connection List ................................................................................................................................ 542 Operand Identifiers and Description Methods ...................................................................................... 553 Surface Mounting Type Soldering Conditions ....................................................................................... 662 Major Differences Between PD78054, 78058F, and 780058 Subseries ........................................... 666 System-Upgrade Method from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ......... 676
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1.1 Features
On-chip high-capacity ROM and RAM
Item Part Number Program Memory Mask ROM Flash Memory -- -- -- -- -- 60 KBNote 1 1,024 bytes 1,024 bytesNote 2 Internal HighSpeed RAM 1,024 bytes Data Memory Internal Buffer RAM 32 bytes Internal Expansion RAM None
PD780053, 780053(A) PD780054, 780054(A) PD780055, 780055(A) PD780056, 780056(A) PD780058, 780058B, 780058B(A) PD78F0058
24 KB 32 KB 40 KB 48 KB 60 KB --
Notes
1. The flash memory capacity can be changed by means of the internal memory size switching register (IMS). 2. The capacity of the internal high-speed RAM can be changed by means of the internal expansion RAM size switching register (IXS).
External memory expansion space: 64 KB Minimum instruction execution time changeable from high-speed (0.4 s: Main system clock 5.0 MHz operation) to ultra-low speed (122 s: Subsystem clock 32.768 kHz operation) Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiple and divide instructions I/O ports: 68 (N-ch open-drain: 4) 8-bit resolution A/D converter: 8 channels (VDD = 1.8 to 5.5 VNote) 8-bit resolution D/A converter: 2 channels (VDD = 1.8 to 5.5 VNote) Serial interface: 3 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel * 3-wire serial I/O mode (on-chip automatic transmit/receive function): 1 channel * 3-wire serial I/O/UART mode (on-chip time-division transfer function): 1 channel Timer: 5 channels * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel Note The operating voltage range of the A/D and D/A converters of the PD780058 is VDD = 2.7 to 5.5 V.
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Vectored interrupt sources: 21 Test inputs: 2 Two types of on-chip clock oscillators (main system clock and subsystem clock) Supply voltage: VDD = 1.8 to 5.5 V (mask ROM version) VDD = 2.7Note to 5.5 V (PD78F0058) Note VDD = 2.2 V can also be supplied to the PD78F0058. For details, contact an NEC Electronics sales representative.
1.2 Applications
Car audio systems, cellular phones, pagers, printers, AV equipment, cameras, PPCs, vending machines, car electrical components, etc.
1.3 Ordering Information
Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Special Special Special Special Special Flash memory Flash memory
PD780053GC-xxx-8BT PD780053GK-xxx-9EU PD780054GC-xxx-8BT PD780054GK-xxx-9EU PD780055GC-xxx-8BT PD780055GK-xxx-9EU PD780056GC-xxx-8BT PD780056GK-xxx-9EU PD780058GC-xxx-8BT PD780058GK-xxx-9EU PD780058BGC-xxx-8BT PD780058BGK-xxx-9EU PD780053GC(A)-xxx-8BT PD780054GC(A)-xxx-8BT PD780055GC(A)-xxx-8BT PD780056GC(A)-xxx-8BT PD780058BGC(A)-xxx-8BT PD78F0058GC-8BT PD78F0058GK-9EU
Remark
xxx indicates ROM code suffix.
For details of the quality grades and their applications, see Quality Grades on NEC Electronics Semiconductor Devices (Document No.: C11531E).
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1.4 Pin Configuration (Top View)
* 80-pin plastic QFP (14 x 14)
PD780053GC-xxx-8BT, 780054GC-xxx-8BT, 780055GC-xxx-8BT, PD780056GC-xxx-8BT, 780058GC-xxx-8BT, 780058BGC-xxx-8BT, PD780053GC(A)-xxx-8BT, 780054GC(A)-xxx-8BT, 780055GC(A)-xxx-8BT, PD780056GC(A)-xxx-8BT, 780058BGC(A)-xxx-8BT, 78F0058GC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12)
PD780053GK-xxx-9EU, 780054GK-xxx-9EU, 780055GK-xxx-9EU, PD780056GK-xxx-9EU, 780058GK-xxx-9EU, 780058BGK-xxx-9EU, 78F0058GK-9EU
P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 VDD0 XT1/P07 XT2 IC (VPP) X1 X2 VDD1 VSS0 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
Cautions 1. Be sure to connect the IC (Internally Connected) pin to VSS0 or VSS1 directly in the normal operating mode. 2. Connect the AVSS pin to VSS0. Remarks 1. The pin connection in parentheses is intended for the PD78F0058. 2. When the PD780053, 780054, 780055, 780056, 780058, or 780058B is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS1 P56/A14 P57/A15 P60 P61 P62 P63 P64/RD
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OUTLINE (PD780058 SUBSERIES)
A8 to A15: AD0 to AD7: ANI0 to ANI7: ANO0, ANO1: ASCK: ASTB: AVREF0, AVREF1: AVSS: BUSY: BUZ: IC: INTP0 to INTP6: P00 to P05, P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P72: P120 to P127: P130, P131:
Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Analog ground Busy Buzzer clock Internally connected Interrupt from peripherals Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13
PCL: RD: RESET: RTP0 to RTP7: RxD0, RxD1: SB0, SB1: SCK0 to SCK2: SI0 to SI2: SO0 to SO2: STB: TI00, TI01: TI1, TI2: TO0 to TO2: TxD0, TxD1: VDD0, VDD1: VPP: VSS0, VSS1: WAIT: WR: X1, X2: XT1, XT2:
Programmable clock Read strobe Reset Real-time output port Receive data Serial bus Serial clock Serial input Serial output Strobe Timer input Timer input Timer output Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
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1.5 78K/0 Series Lineup
78K/0 Series product lineup is illustrated below. Part numbers in the boxes indicate subseries names.
Products in mass production Products under development
Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS
PD780024AS PD78014H
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited functions
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A
52-pin version of the PD780024A EMI-noise reduced version of the PD78018F
PD78018F PD78083
Inverter control
PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
78K/0 Series
100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780354Y PD780344Y
PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer.
Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBusTM controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
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The following lists the main functional differences between subseries products. * Non-Y subseries
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Value Expansion 1.8 V
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
2 ch 3 ch (UART: 1 ch)
88
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - 4 ch 8 ch - 4 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K PD780034A 8 K to 32 K PD780024A PD780034AS PD780024AS PD78014H PD78018F 8 K to 60 K PD78083
8 K to 16 K - - - 1 ch - 8 ch
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
39
-
2 ch
53
1 ch (UART: 1 ch) - 3 ch (UART: 2 ch)
33 47 4.0 V
- -
Inverter PD780988 16 K to 60 K 3 ch Note control VFD drive
PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780354 24 K to 32 K 4 ch PD780344 PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
1 ch
1 ch
1 ch
- 8 ch
8 ch -
-
3 ch (UART: 1 ch)
66
1.8 V
-
2 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
supported PD780816 32 K to 60 K Meter control Dashboard control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch PD780828B 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch)
56 59
4.0 V
-
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
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1.6 Block Diagram
TO0/P30 TI00/P00 TI01/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit timer/ event counter P00 P01 to P05 P07
Port 0
8-bit timer/ event counter 1
Port 1
P10 to P17
8-bit timer/ event counter 2
Port 2
P20 to P27
Watchdog timer
Port 3
P30 to P37
Watch timer
Port 4
P40 to P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 78K/0 CPU core ROM (flash memory) Serial interface 0
Port 5
P50 to P57
Port 6
P60 to P67
SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24
Serial interface 1 Port 7 P70 to P72
BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10 to ANI7/P17 AVSS AVREF0 A/D converter Serial interface 2 RAM
Port 12
P120 to P127
Port 13
P130, P131
Real-time output port
RTP0/P120 to RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF1 D/A converter External access
AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 Interrupt control
INTP0/P00 to INTP5/P05
BUZ/P36
RESET Buzzer output System control X1 X2 XT1/P07 XT2
PCL/P35
Clock output control
VDD0, VDD1
VSS0, VSS1
IC (VPP)
Remarks 1. The internal ROM and RAM capacities depend on the product. 2. The pin connection in parentheses is intended for the PD78F0058.
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1.7 Outline of Function
Part Number Item Internal memory ROM
PD780053, PD780054, PD780055, PD780056, PD780058B, PD780058 PD78F0058 780053(A) 780054(A) 780055(A) 780056(A) 780058B(A)
Mask ROM 24 KB 32 KB 40 KB 48 KB 60 KB Flash memory 60 KBNote 1
High-speed RAM Buffer RAM Expansion RAM Memory space General-purpose registers Minimum instruction execution time With main system clock selected
1,024 bytes 32 bytes None 64 KB 8 bits x 8 x 4 banks Function to vary minimum instruction execution time incorporated 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz operation) 1,024 bytes 1,024 bytesNote 2
With subsystem clock selected 122 s (@ 32.768 kHz operation) Instruction set * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, and boolean operation) BCD adjust, etc. 68
I/O ports
Total:
* CMOS input: 2 * CMOS I/O: 62 * N-ch open-drain I/O: 4 A/D converter Operating voltage range D/A converter Operating voltage range Serial interface 8-bit resolution x 8 channels VDD = 1.8 to 5.5 V 8-bit resolution x 2 channels VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V
* 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible: 1 channel * 3-wire serial I/O mode (on-chip max. 32 bytes auto-transmit/receive function): 1 channel * 3-wire serial I/O/UART mode (on-chip time-division transfer function) selectable: 1 channel * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 channel channels channel channel
Timer
Timer outputs Clock output
3: (14-bit PWM output enable: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (main system clock: @ 5.0 MHz operation) 32.768 kHz (subsystem clock: @ 32.768 kHz operation) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (main system clock: @ 5.0 MHz operation)
Buzzer output
Notes
1. The capacity of the flash memory can be changed by using the internal memory switching register (IMS). 2. The capacity of the internal expansion RAM can be changed by using the internal expansion RAM size switching register (IXS).
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Item Vectored interrupt sources Test input Supply voltage
Part Number PD780053, PD780054, PD780055, PD780056, PD780058B, PD780058 PD78F0058 780053(A) 780054(A) 780055(A) 780056(A) 780058B(A) Maskable Non-maskable Software Internal: 13, External: 6 Internal: 1 1 Internal: 1, External: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (fine pitch) (12 x 12) VDD = 2.7Note to 5.5 V
Operating ambient temperature Package
Note
VDD = 2.2 V can also be supplied. For details, contact an NEC Electronics sales representative.
The timers are outlined below.
16-Bit Timer/ Event Counter Operating Interval timer Mode Function External event counter Timer output PWM output Pulse width measurement Square-wave output One-shot pulse output Interrupt request Test input 2 channelsNote 3 --
8-Bit Timer/Event Counters 1 and 2 2 channels -- -- -- --
Watch Timer
Watchdog Timer
1 channelNote 1 -- -- -- -- -- --
1 channelNote 2 -- -- -- -- -- -- --
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer can perform either the watchdog timer function or the interval timer function. 3. When capture/compare registers 00 and 01 (CR00 and CR01) are specified as compare registers.
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1.8 Mask Options
The mask ROM versions (PD780053, 780053(A), 780054, 780054(A), 780055, 780055(A), 780056, 780056(A), 780058, 780058B, 780058B(A)) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. The mask options provided in the PD780058 Subseries are shown in Table 1-1. Table 1-1. Mask Options of Mask ROM Versions
Pin Names P60 to P63 Mask Options Pull-up resistor connection can be specified in 1-bit units.
1.9 Differences Between Standard Model and (A) Model
The (A) models of the PD780058 Subseries (PD780053(A), 780054(A), 780055(A), 780056(A), and 780058B(A)) have improved reliability by increasing the check items from the standard model (PD780053, 780054, 780055, 780056, and 780058B). The functions and electrical characteristics of the (A) model are the same as those of the standard model. Table 1-2. Differences Between Standard Model and (A) Model
Product Name Item Quality grade Standard Special (for general-purpose electronic systems) (for high-reliability electronic systems) Standard Model (A) Model
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2.1 Features
On-chip high-capacity ROM and RAM
Item Part Number Program Memory Mask ROM Flash Memory -- -- -- -- -- 60 KBNote 1 1,024 bytes 1,024 bytesNote 2 Internal HighSpeed RAM 1,024 bytes Data Memory Internal Buffer RAM 32 bytes Internal Expansion RAM None
PD780053Y, 780053Y(A) PD780054Y, 780054Y(A) PD780055Y, 780055Y(A) PD780056Y, 780056Y(A) PD780058BY, 780058BY(A) PD78F0058Y
24 KB 32 KB 40 KB 48 KB 60 KB --
Notes
1. The capacity of flash memory can be changed by means of the internal memory size switching register (IMS). 2. The capacity of internal high-speed RAM can be changed by means of the internal expansion RAM size switching register (IXS).
External memory expansion space: 64 KB Minimum instruction execution time changeable from high-speed (0.4 s: Main system clock 5.0 MHz operation) to ultra-low speed (122 s: Subsystem clock 32.768 kHz operation) Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiple and divide instructions I/O ports: 68 (N-ch open-drain: 4) 8-bit resolution A/D converter: 8 channels (VDD = 1.8 to 5.5 V) 8-bit resolution D/A converter: 2 channels (VDD = 1.8 to 5.5 V) Serial interface: 3 channels * 3-wire serial I/O/2-wire serial I/O/I2C bus mode: 1 channel * 3-wire serial I/O mode (on-chip automatic transmit/receive function): 1 channel * 3-wire serial I/O/UART mode (on-chip time-division transfer function): 1 channel Timer: 5 channels * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel Vectored interrupt sources: 21 Test inputs: 2 Two types of on-chip clock oscillators (main system clock and subsystem clock) Supply voltage: VDD = 1.8 to 5.5 V (mask ROM version) VDD = 2.7Note to 5.5 V (PD78F0058Y) Note VDD = 2.2 V can also be supplied to the PD78F0058Y. For details, contact an NEC Electronics sales representative.
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2.2 Applications
Car audio systems, cellular phones, pagers, printers, AV equipment, cameras, PPCs, vending machines, car electrical components, etc.
2.3 Ordering Information
Part Number Package 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic TQFP (fine pitch) (12 x 12) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Special Special Special Special Special Flash-memory Flash-memory
PD780053YGC-xxx-8BT PD780053YGK-xxx-9EU PD780054YGC-xxx-8BT PD780054YGK-xxx-9EU PD780055YGC-xxx-8BT PD780055YGK-xxx-9EU PD780056YGC-xxx-8BT PD780056YGK-xxx-9EU PD780058BYGC-xxx-8BT PD780058BYGK-xxx-9EU PD780053YGC(A)-xxx-8BT PD780054YGC(A)-xxx-8BT PD780055YGC(A)-xxx-8BT PD780056YGC(A)-xxx-8BT PD780058BYGC(A)-xxx-8BT PD78F0058YGC-8BT PD78F0058YGK-9EU
Remark
Note Note
xxx indicates ROM code suffix.
For details of the quality grades and their applications, see Quality Grades on NEC Electronics Semiconductor Devices (Document No.: C11531E).
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2.4 Pin Configuration (Top View)
* 80-pin plastic QFP (14 x 14)
PD780053YGC-xxx-8BT, 780054YGC-xxx-8BT, 780055YGC-xxx-8BT, PD780056YGC-xxx-8BT, 780058BYGC-xxx-8BT, 780053YGC(A)-xxx-8BT, PD780054YGC(A)-xxx-8BT, 780055YGC(A)-xxx-8BT, 780056YGC(A)-xxx-8BT, PD780058BYGC(A)-xxx-8BT, 78F0058YGC-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12)
PD780053YGK-xxx-9EU, 780054YGK-xxx-9EU, 780055YGK-xxx-9EU, PD780056YGK-xxx-9EU, 780058BYGK-xxx-9EU, 78F0058YGK-9EU
P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVREF0 VDD0 XT1/P07 XT2 IC (VPP) X1 X2 VDD1 VSS0 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P40/AD0 P41/AD1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
Cautions 1. Be sure to connect the IC (Internally Connected) pin to VSS0 directly in the normal operating mode. 2. Connect the AVSS pin to VSS0. Remarks 1. The pin connection in parentheses is intended for the PD78F0058Y. 2. When the PD780053Y, 780054Y, 780055Y, 780056Y, or 780058BY is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS1 P56/A14 P57/A15 P60 P61 P62 P63 P64/RD
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A8 to A15: AD0 to AD7: ANI0 to ANI7: ANO0, ANO1: ASCK: ASTB: AVREF0, AVREF1: AVSS: BUSY: BUZ: IC: INTP0 to INTP6: P00 to P05, P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P67: P70 to P72: P120 to P127: P130, P131: PCL:
Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Analog ground Busy Buzzer clock Internally connected Interrupt from peripherals Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 Programmable clock
RD: RESET: RTP0 to RTP7: RxD0, RxD1: SB0, SB1: SCK0 to SCK2: SCL: SDA0, SDA1: SI0 to SI2: SO0 to SO2: STB: TI00, TI01: TI1, TI2: TO0 to TO2: TxD0, TxD1: VDD0, VDD1: VPP: VSS0, VSS1: WAIT: WR: X1, X2: XT1, XT2:
Read strobe Reset Real-time output port Receive data Serial bus Serial clock Serial clock Serial data Serial input Serial output Strobe Timer input Timer input Timer output Transmit data Power supply Programming power supply Ground Wait Write strobe Crystal (main system clock) Crystal (subsystem clock)
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2.5 78K/0 Series Lineup
78K/0 Series product lineup is illustrated below. Part numbers in the boxes indicate subseries names.
Products in mass production Products under development
Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS
PD780024AS PD78014H
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited functions
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A
52-pin version of the PD780024A EMI-noise reduced version of the PD78018F
PD78018F PD78083
Inverter control
PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter control circuit and UART. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
78K/0 Series
100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780354Y PD780344Y
PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer.
Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703Y PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBus controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
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Major functional differences among the Y subseries are shown below. * Y subseries
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Value Expansion 1.8 V 2.7 V
PD78078Y 48 K to 60 K 4 ch
PD78070AY
-
2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88 61 - 3 ch (I C: 1 ch)
2 2
PD780018AY 48 K to 60 K
88 68 69 1.8 V 2.7 V 2.0 V
PD780058Y 24 K to 60 K 2 ch
PD78058FY 48 K to 60 K
2 ch 3 ch (time-division UART: 1 ch, I C: 1 ch) 3 ch (UART: 1 ch, I C: 1 ch)
2
PD78054Y 16 K to 60 K
PD780078Y 48 K to 60 K
PD780034AY 8 K to 32 K PD780024AY
2 ch 1 ch 8 ch - 2 ch (I2C: 1 ch) 1 ch 1 ch 1 ch - 8 ch 8 ch - - 4 ch (UART: 1 ch, I C: 1 ch) 3 ch (time-division UART: 1 ch, I2C: 1 ch) 2 ch (UART: 1 ch, I C: 1 ch) 3 ch 2 ch 1 ch 1 ch 16 ch - - 4 ch (UART: 1 ch, I2C: 1 ch) 67
2 2
-
8 ch
-
4 ch (UART: 2 ch, I C: 1 ch)
2
2
52
1.8 V
3 ch (UART: 1 ch, I C: 1 ch) 51
PD78018FY 8 K to 60 K
LCD drive
53 66 1.8 V -
PD780354Y 24 K to 32 K 4 ch PD780344Y PD780308Y 48 K to 60 K 2 ch
57
2.0 V
PD78064Y 16 K to 32 K
Bus PD780701Y 60 K interface PD780703Y supported PD780833Y
3.5 V
-
65
4.5 V
Remark
Functions other than the serial interface are common to both the Y and non-Y subseries.
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2.6 Block Diagram
TO0/P30 TI00/P00 TI01/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 16-bit timer/ event counter P00 P01 to P05 P07
Port 0
8-bit timer/ event counter 1
Port 1
P10 to P17
8-bit timer/ event counter 2
Port 2
P20 to P27
Watchdog timer
Port 3
P30 to P37
Watch timer
Port 4
P40 to P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 78K/0 CPU core ROM (flash memory) Serial interface 0
Port 5
P50 to P57
Port 6
P60 to P67
SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24
Serial interface 1 Port 7 P70 to P72
BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10 to ANI7/P17 AVSS AVREF0 A/D converter Serial interface 2 RAM
Port 12
P120 to P127
Port 13
P130, P131
Real-time output port
RTP0/P120 to RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF1 D/A converter External access
AD0/P40 to AD7/P47 A8/P50 to A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 Interrupt control
INTP0/P00 to INTP5/P05
BUZ/P36
RESET Buzzer output System control X1 X2 XT1/P07 XT2
PCL/P35
Clock output control
VDD0, VDD1
VSS0, VSS1
IC (VPP)
Remarks 1. The internal ROM and RAM capacities depend on the product. 2. The pin connection in parentheses is intended for the PD78F0058Y.
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2.7 Outline of Functions
Part Number Item Internal memory ROM
PD780053Y, PD780054Y, PD780055Y, PD780056Y, PD780058BY PD78F0058Y 780053Y(A) 780054Y(A) 780055Y(A) 780056Y(A) 780058BY(A)
Mask ROM 24 KB 32 KB 40 KB 48 KB 60 KB Flash memory 60 KBNote 1
High-speed RAM Buffer RAM Expansion RAM Memory space General-purpose registers Minimum instruction execution time With main system clock selected With subsystem clock selected Instruction set
1,024 bytes 32 bytes None 64 KB 8 bits x 8 x 4 banks Function to vary minimum instruction execution time incorporated 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz operation) 122 s (@ 32.768 kHz operation) * * * * 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, and boolean operation) BCD adjust, etc. 68 2 62 4 1,024 bytes 1,024 bytesNote 2
I/O ports
Total: * CMOS input: * CMOS I/O: * N-ch open-drain I/O:
A/D converter Operating voltage range D/A converter Operating voltage range Serial interface
8-bit resolution x 8 channels VDD = 1.8 to 5.5 V 8-bit resolution x 2 channels VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V
* 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible: 1 channel * 3-wire serial I/O mode (on-chip max. 32 bytes auto-transmit/receive function): 1 channel * 3-wire serial I/O/UART mode (on-chip time-division transfer function) selectable: 1 channel * * * * 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: 1 2 1 1 channel channels channel channel
Timer
Timer outputs Clock output
3: (14-bit PWM output enable: 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (main system clock: @ 5.0 MHz operation) 32.768 kHz (subsystem clock: @ 32.768 kHz operation) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (main system clock: @ 5.0 MHz operation)
Buzzer output
Notes
1. The capacity of the flash memory can be changed by using the internal memory switching register (IMS). 2. The capacity of the internal expansion RAM can be changed by using the internal expansion RAM size switching register (IXS).
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Part Number Item Vectored interrupt sources Test input Supply voltage Operating ambient temperature Package Maskable Non-maskable Software
PD780053Y, PD780054Y, PD780055Y, PD780056Y, PD780058BY PD78F0058Y 780053Y(A) 780054Y(A) 780055Y(A) 780056Y(A) 780058BY(A)
Internal: 13, External: 6 Internal: 1 1 Internal: 1, External: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (Fine pitch) (12 x 12) VDD = 2.7Note to 5.5 V
Note
VDD = 2.2 V can also be supplied. For details, contact an NEC Electronics sales representative.
The timers are outlined below.
16-Bit Timer/ Event Counter Operating Interval timer Mode Function External event counter Timer output PWM output Pulse width measurement Square-wave output One-shot pulse output Interrupt request Test input 2 channelsNote 3 --
8-Bit Timer/Event Counters 1 and 2 2 channels -- -- -- --
Watch Timer
Watchdog Timer
1 channelNote 1 -- -- -- -- -- --
1 channelNote 2 -- -- -- -- -- -- --
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer can perform either the watchdog timer function or the interval timer function. 3. When capture/compare registers 00 and 01 (CR00 and CR01) are specified as compare registers.
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2.8 Mask Options
The mask ROM versions (PD780053Y, 780053Y(A), 780054Y, 780054Y(A), 780055Y, 780055Y(A), 780056Y, 780056Y(A), 780058BY, 780058BY(A)) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production. Using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. The mask options provided in the PD780058Y Subseries are shown in Table 2-1. Table 2-1. Mask Options of Mask ROM Versions
Pin Names P60 to P63 Mask Options Pull-up resistor connection can be specified in 1-bit units.
2.9 Differences Between Standard Model and (A) Model
The (A) models of the PD780058Y Subseries (PD780053Y(A), 780054Y(A), 780055Y(A), 780056Y(A), and 780058BY(A)) have improved reliability by increasing the check items from the standard model (PD780053Y, 780054Y, 780055Y, 780056Y, and 780058BY). The functions and electrical characteristics of the (A) model are the same as those of the standard model. Table 2-2. Differences Between Standard Model and (A) Model
Product Name Item Quality grade Standard Special (for general-purpose electronic systems) (for high-reliability electronic systems) Standard Model (A) Model
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3.1 Pin Function List
(1) Port pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10 to P17 Input I/O Input only Port 1 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.Note 2 Port 2 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Input Input I/O Input I/O Port 0 7-bit I/O port Function Input only Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. After Reset Alternate Function Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37
I/O
Input
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0 SO0/SB1 SCK0
I/O
Port 3 8-bit I/O port Input/output can be specified in 1-it units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Notes
1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the feedback resistor incorporated in the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to the input mode. In this case, any connected on-chip pull-up resistors are automatically disabled.
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(1) Port pins (2/2)
Pin Name P40 to P47 I/O I/O Function Port 4 8-bit I/O port Input/output can be specified in 8-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. The test input flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit I/O port LEDs can be driven directly. Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 6 8-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain I/O port On-chip pull-up resistors can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. If used as an input port, an on-chip pull-up resistor can be connected by setting software. After Reset Alternate Function Input AD0 to AD7
P50 to P57
I/O
Input
A8 to A15
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P120 to P127
I/O
Input
--
RD WR WAIT ASTB
I/O
Port 7 3-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 12 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 13 2-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
Input
SI2/RxD0 SO2/TxD0 SCK2/ASCK
I/O
Input
RTP0 to RTP7
P130 to P131
I/O
Input
ANO0 to ANO1
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(2) Non-port pins (1/2)
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI1 SI2 SO0 SO1 SO2 SB0 SB1 SCK0 SCK1 SCK2 STB BUSY RxD0 RxD1 TxD0 TxD1 ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ RTP0 to RTP7 Output Output Output Output Input Input Asynchronous serial interface serial clock input External count clock input to 16-bit timer (TM0) Capture trigger signal input to capture register (CR00) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) 16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for main system clock and subsystem clock trimming) Buzzer output Real-time output port outputting data in synchronization with trigger Input Input Input Input Input Input Output Asynchronous serial interface serial data output Input Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Asynchronous serial interface serial data input Input Input Input I/O Serial interface serial clock input/output Input I/O Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input I/O Input Function External interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). After Reset Alternate Function Input P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0 P20 P70/RxD P26/SB1 P21 P71/TxD P25/SI0 P26/SO0 P27 P22 P72/ASCK P23/TxD1 P24/RxD1 P70/SI2 P24/BUSY P71/SO2 P23/STB P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 P120 to P127
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(2) Non-port pins (2/2)
Pin Name AD0 to AD7 A8 to A15 RD WR WAIT ASTB Input Output I/O I/O Output Output Function Lower address/data bus when expanding memory externally Higher address bus when expanding memory externally Strobe signal output for read operation from external memory Strobe signal output for write operation to external memory Wait insertion when accessing external memory Strobe output externally latching address information output to ports 4 and 5 to access external memory A/D converter analog input D/A converter analog output A/D converter reference voltage input (also functions as analog power supply) D/A converter reference voltage input A/D converter, D/A converter ground potential. Use the same potential as VSS0. System reset input Crystal connection for main system clock oscillation Input Input After Reset Alternate Function Input Input Input P40 to P47 P50 to P57 P64 P65 P66 P67
ANI0 to ANI7
Input
Input Input --
P10 to P17 P130, P131 --
ANO0, ANO1 Output AVREF0 Input
AVREF1 AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP IC
Input -- Input Input -- Input -- -- -- -- -- -- --
-- -- -- -- --
-- -- -- -- -- P07 -- -- -- -- -- -- --
Crystal connection for subsystem clock oscillation
Input --
Positive power supply for ports Ground potential for ports Positive power supply (except ports and analog block) Ground potential (except ports and analog block) High-voltage application for program write/verify. Internally connected. Connect directly to VSS0.
-- -- -- -- -- --
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3.2 Description of Pin Functions
3.2.1 P00 to P05, P07 (Port 0) P00 to P05 and P07 function as a 7-bit I/O port. Besides serving as I/O port pins, they also function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified in 1-bit units. (1) Port mode P00 and P07 function as input-only port pins and P01 to P05 function as I/O port pins. P01 to P05 can be specified as input or output in 1-bit units using port mode register 0 (PM0). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode In this mode, P00 to P05 and P07 function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP5 INTP0 to INTP5 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). INTP0 or INTP1 become 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (b) TI00 This is a pin for inputting the external count clock to the 16-bit timer/event counter. (c) TI01 This is a pin for inputting the capture trigger signal to the capture register (CR00) of the 16-bit timer/event counter. (d) XT1 This is a crystal connection pin for subsystem clock oscillation. 3.2.2 P10 to P17 (Port 1) P10 to P17 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an A/D converter analog inputs. The following operating modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 1 (PM1). When they are used as input port pins, on-chip pull-up resistor can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P10 to P17 function as A/D converter analog input pins (ANI0 to ANI7). On-chip pull-up resistors are automatically disabled when these pins are specified as analog inputs.
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3.2.3 P20 to P27 (Port 2) P20 to P27 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as data input/output to/from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output. The following operating modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 2 (PM2). When they are used as input ports, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P20 to P27 function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) SI0, SI1, SO0, SO1 These are serial data I/O pins of the serial interface. (b) SCK0, SCK1 These are serial clock I/O pins of the serial interface. (c) SB0, SB1 These are NEC Electronics standard serial bus interface I/O pins. (d) BUSY This is an automatic transmit/receive busy input pin of the serial interface. (e) STB This is an automatic transmit/receive strobe output pin of the serial interface. (f) RxD1, TxD1 These are serial interface serial data I/O pins of the asynchronous serial interface. Caution When P20 to P27 are used as serial interface pins, the I/O and output latches must be set according to the function the user requires. For the setting, see Figure 16-4 Format of Serial Operation Mode Register 0, Figure 18-3 Format of Serial Operation Mode Register 1, and Table 19-2 Serial Interface Channel 2 Operating Mode Settings.
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3.2.4 P30 to P37 (Port 3) P30 to P37 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as timer input/output, clock output and buzzer output. The following operating modes can be specified in 1-bit units. (1) Port mode P30 to P37 function as an 8-bit I/O port. They can be specified as an input or output in 1-bit units using port mode register 3 (PM3). When they are used as input port pins, on-chip pull-up resistors can be connected to then using pull-up resistor option register L (PUOL). (2) Control mode P30 to P37 function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 These are pins for inputting the external count clock to the 8-bit timer/event counter. (b) TO0 to TO2 These are timer output pins. (c) PCL This is a clock output pin. (d) BUZ This is a buzzer output pin. 3.2.5 P40 to P47 (Port 4) P40 to P47 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating modes can be specified in 8-bit units. (1) Port mode P40 to P47 using function as an 8-bit I/O port. They can be specified for as input or output in 8-bit units using the internal memory expansion mode register (MM). When they are used as an input port pins, on-chip pullup resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P40 to P47 function as the lower address/data bus pins (AD0 to AD7) in external memory expansion mode. When these pins are used as an address/data bus, on-chip pull-up resistors are automatically disabled.
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3.2.6 P50 to P57 (Port 5) P50 to P57 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an address bus. P50 to P57 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P50 to P57 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 5 (PM5). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P50 to P57 function as the higher address bus pins (A8 to A15) in external memory expansion mode. When these pins are used as an address bus, on-chip pull-up resistors are automatically disabled. 3.2.7 P60 to P67 (Port 6) P60 to P67 function as an 8-bit I/O port. Besides serving as I/O port pins, they are also used for control in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P60 to P67 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain outputs. In mask ROM products, on-chip pull-up resistors can be connected to these pins using a mask option. When P64 to P67 are used as input port pins, on-chip pull-up resistor can be connected using pull-up resistor option register L (PUOL). (2) Control mode P60 to P67 function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. When pins are used as control signal outputs, on-chip pull-up resistors are automatically disabled. Caution When an external wait is not used in external memory expansion mode, P66 can be used as an I/O port pins.
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3.2.8 P70 to P72 (Port 7) P70 to P72 function as a 3-bit I/O port. Besides serving as I/O port pins, they also function as serial interface data I/O and clock I/O. The following operating modes can be specified in 1-bit units. (1) Port mode P70 to P72 function as a 3-bit I/O port. They can be specified as input port or output in 1-bit units using port mode register 7 (PM7). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P70 to P72 function as serial interface data I/O and clock I/O. (a) SI2, SO2 These are serial data I/O pins of the serial interface. (b) SCK2 This is a serial clock I/O pin of the serial interface. (c) RxD0, TxD0 These are serial data I/O pins of the asynchronous serial interface. (d) ASCK This is a serial clock I/O pin of the asynchronous serial interface. Caution When P70 to P72 are used as serial interface pins, the I/O and output latches must be set according to the function the user requires. For the setting, see the operation mode setting list in Table 19-2 Serial Interface Channel 2. 3.2.9 P120 to P127 (Port 12) P120 to P127 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as a real-time output port. The following operating modes can be specified in 1-bit units. (1) Port mode P120 to P127 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 12 (PM12). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register H (PUOH). (2) Control mode P120 to P127 function as a real-time output port (RTP0 to RTP7) that outputs data in synchronization with a trigger.
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3.2.10 P130 and P131 (Port 13) P130 and P131 function as a 2-bit I/O port. Besides serving as I/O port pins, they also function as D/A converter analog output. The following operating modes can be specified in 1-bit units. (1) Port mode P130 and P131 function as a 2-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 13 (PM13). When they are used as an input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register H (PUOH). (2) Control mode P130 and P131 function as D/A converter analog outputs (ANO0 and ANO1). Caution When only one of the D/A converter channels is used with AVREF1 < VDD0, the other pins that are not used as analog outputs must be set as follows: * * Set the PM13x bit of port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS0. Clear the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. 3.2.11 AVREF0 This is the A/D converter reference voltage input pin. This pin also serves as an analog power supply pin. Supply power to this pin when the A/D converter is used. When the A/D converter is not used, use the same voltage that of the VDD0 or VSS0 pin. 3.2.12 AVREF1 This is the D/A converter reference voltage input pin. When the D/A converter is not used, use the same voltage that of the VDD0 pin. 3.2.13 AVSS This is the ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS0 pin even when the A/D converter or D/A converter is not used. 3.2.14 RESET This is the low-level active system reset input pin. 3.2.15 X1 and X2 These are crystal resonator connection pins for main system clock oscillation. For external clock supply, input a signal to X1 and its inverted signal to X2. 3.2.16 XT1 and XT2 These are crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input a signal to XT1 and its inverted signal to XT2. 3.2.17 VDD0, VDD1 VDD0 is the positive power supply pin for ports. VDD1 is the positive power supply pin for blocks other than port and analog blocks.
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3.2.18 VSS0, VSS1 VSS0 is the ground potential pin for ports. VSS1 is the ground potential pin for blocks other than port and analog blocks. 3.2.19 VPP (Flash memory version only) This is the high-voltage application pin for flash memory programming mode setting and program write/verify. Connect this pin in either of the following ways. * Connect independently to a 10 k pull-down resistor. * By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to VSS0 in the normal operation mode. 3.2.20 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD780058 Subseries at delivery. Connect it directly to VSS0 with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS0 pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. Connect the IC pin to VSS0 directly.
VSS0 IC
As short as possible
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3.3 I/O Circuits and Recommended Connection of Unused Pins
Table 3-1 shows the pin I/O circuit types and the recommended connection of unused pins. Refer to Figure 3-1 for the configuration of the I/O circuit of each type. Table 3-1. Pin I/O Circuit Types (1/2)
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 5-N 5-H I/O I/O Input: Independently connect to VDD0 via a resistor. Output: Leave open. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. 5-H 8-C 5-H 16 11-D 8-C 5-H 8-C 5-H 8-C 10-B Input I/O Connect to VDD0. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. I/O Circuit Type 2 8-C I/O Input I/O Recommended Connection of Unused Pins Connect to VSS0. Input: Independently connect to VSS0 via a resistor. Output: Leave open.
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Table 3-1. Pin I/O Circuit Types (2/2)
Pin Name P60 to P63 (mask ROM version) P60 to P63 (flash memory version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET XT2 AVREF0 AVREF1 AVSS IC (mask ROM version) VPP (flash memory version) 8-C 5-H 8-C 5-H 12-C 2 16 -- I/O Input -- Leave open. Connect to VDD0 or VSS0. Connect to VDD0. Connect to VSS0. Connect directly to VSS0. Independently connect via a 10 k pull-down resistor, or connect to VSS0 or VSS1 directly. Input: Independently connect to VSS0 via a resistor. Output: Leave open. -- I/O Circuit Type 13-J 13-K 5-H I/O I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VDD0 via a resistor. Output: Set 0 to the port and leave open at low level output. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open.
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Figure 3-1. Pin I/O Circuit List (1/2)
Type 2 Type 8-C VDD0
Pull-up enable IN VDD0 Data Schmitt-triggered input with hysteresis characteristics P-ch
P-ch
IN/OUT Output disable N-ch VSS0
Type 5-H
VDD0
Type 10-B
VDD0
Pull-up enable VDD0 Data P-ch
P-ch
Pull-up enable VDD0 Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch VSS0
Output disable
N-ch VSS0
Input enable Type 5-N VDD0 Type 11-D Pull-up enable Data VDD0 P-ch VDD0 P-ch IN/OUT P-ch IN/OUT Output disable N-ch VSS0 Input enable Output disable Comparator + - N-ch P-ch VSS0
Pull-up enable VDD0 Data
P-ch
N-ch VSS0 VREF (threshold voltage)
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Figure 3-1. Pin I/O Circuit List (2/2)
Type 12-C VDD0 Type 13-K IN/OUT P-ch VDD0 P-ch IN/OUT Output disable Input enable P-ch Analog output voltage N-ch Type 16 Feedback cut-off IN/OUT Data Output disable VSS0 VDD0 RD P-ch XT1 Medium breakdown input buffer XT2 N-ch P-ch N-ch VSS0 RD Data Output disable VSS0 VDD0 P-ch N-ch
Pull-up enable Data
Medium breakdown input buffer
Type 13-J Mask option
VDD0
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4.1 Pin Function List
(1) Port pins (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10 to P17 Input I/O Input only Port 1 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting softwareNote 2. Port 2 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Input Input I/O Input I/O Port 0 7-bit I/O port Function Input only Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. After Reset Alternate Function Input Input INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37
I/O
Input
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
I/O
Port 3 8-bit I/O port Input/output mode can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Notes
1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the feedback resistor incorporated in the subsystem clock oscillator). 2. When pins P10/ANI0 to P17/ANI7 are used as an analog input of the A/D converter, set port 1 to the input mode. In this case, any connected on-chip pull-up resistors are automatically disabled.
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(1) Port pins (2/2)
Pin Name P40 to P47 I/O I/O Function Port 4 8-bit I/O port Input/output can be specified in 8-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. The test input flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit I/O port LEDs can be driven directly. Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P120 to P127 I/O I/O Port 7 3-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 12 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 13 2-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Input I/O Port 6 8-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain I/O port On-chip pull-up resistors can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Input -- After Reset Alternate Function Input AD0 to AD7
P50 to P57
I/O
Input
A8 to A15
RD WR WAIT ASTB SI2/RxD0 SO2/TxD0 SCK2/ASCK Input RTP0 to RTP7
P130 to P131
I/O
Input
ANO0 to ANO1
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(2) Non-port pins (1/2)
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI1 SI2 SO0 SO1 SO2 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCK2 SCL STB BUSY RxD0 RxD1 TxD TxD1 ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ RTP0 to RTP7 Output Output Output Output Input Input Asynchronous serial interface serial clock input External count clock input to 16-bit timer (TM0) Capture trigger signal input to capture register (CR00) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) 16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for main system clock and subsystem clock trimming) Buzzer output Real-time output port outputting data in synchronization with trigger Input Input Input Input Input Input Output Asynchronous serial interface serial data output Input Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Asynchronous serial interface serial data input Input Input Input I/O Serial interface serial clock input/output Input I/O Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input I/O Input Function External interrupt request inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). After Reset Alternate Function Input P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0/SDA0 P20 P70/RxD P26/SB1/SDA1 P21 P71/TxD P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P72/ASCK P27/SCK0 P23/TxD1 P24/RxD1 P70/SI2 P24/BUSY P71/SO2 P23/STB P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 P120 to P127
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(2) Non-port pins (2/2)
Pin Name AD0 to AD7 A8 to A15 RD WR WAIT ASTB Input Output I/O I/O Output Output Function Lower address/data bus when expanding memory externally Higher address bus when expanding memory externally Strobe signal output for read operation from external memory Strobe signal output for write operation to external memory Wait insertion when accessing external memory Strobe output externally latching address information output to ports 4 and 5 to access external memory A/D converter analog input D/A converter analog output A/D converter reference voltage input (also functions as analog power supply) D/A converter reference voltage input A/D converter, D/A converter ground potential. Use the same potential as VSS0. System reset input Crystal connection for main system clock oscillation Input Input After Reset Alternate Function Input Input Input P40 to P47 P50 to P57 P64 P65 P66 P67
ANI0 to ANI7
Input
Input Input -- -- -- -- -- --
P10 to P17 P130, P131 -- -- -- -- -- -- P07 -- -- -- -- -- -- -- --
ANO0, ANO1 Output AVREF0 AVREF1 AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP VSS IC Input Input -- Input Input -- Input -- -- -- -- -- -- -- --
Crystal connection for subsystem clock oscillation
Input --
Positive power supply for ports Ground potential for ports Positive power supply (except ports and analog block) Ground potential (except ports and analog block) High-voltage application for program write/verify. Ground potential Internally connected. Connect directly to VSS0.
-- -- -- -- -- -- --
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4.2 Description of Pin Functions
4.2.1 P00 to P05, P07 (Port 0) P00 to P05 and P07 function as a 7-bit I/O port. Besides serving as I/O port pins, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. The following operating modes can be specified in 1-bit units. (1) Port mode P00 and P07 function as input-only port pins and P01 to P05 function as I/O port pins. P01 to P05 can be specified as input or output in 1-bit units using port mode register 0 (PM0). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode In this mode, P00 to P05 and P07 function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP5 INTP0 to INTP5 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). INTP0 and INTP1 become a 16-bit timer/event counter capture trigger signal input pins with a valid edge input. (b) TI00 This is a pin for inputting the external count clock to the 16-bit timer/event counter. (c) TI01 This is a pin for inputting the capture trigger signal to the capture register (CR00) of the 16-bit timer/event counter. (d) XT1 This is a crystal connection pin for subsystem clock oscillation.
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4.2.2 P10 to P17 (Port 1) P10 to P17 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an A/D converter analog inputs. The following operating modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 1 (PM1). When they are used as input port pins, on-chip pull-up resistor can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P10 to P17 function as A/D converter analog input pins (ANI0 to ANI7). On-chip pull-up resistors are automatically disabled when these pins are specified as analog inputs. 4.2.3 P20 to P27 (Port 2) P20 to P27 an 8-bit I/O port. Besides serving as I/O port pins, they also function as data input/output to/from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output. The following operating modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 2 (PM2). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P20 to P27 function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. (a) SI0, SI1, SO0, SO1, SB0, SB1, SDA0, SDA1 These are serial data I/O pins of the serial interface. (b) SCK0, SCK1, SCL These are serial clock I/O pins of the serial interface. (c) BUSY This is an automatic transmit/receive busy input pin of the serial interface. (d) STB This is an automatic transmit/receive strobe output pin of the serial interface. (e) RxD1, TxD1 These are serial interface serial data I/O pins of the asynchronous serial interface. Caution When P20 to P27 are used as a serial interface pins, the I/O and output latches must be set according to the function the user requires. For the setting, see Figure 17-4 Format of Serial Operation Mode Register 0, Figure 18-3 Format of Serial Operation Mode Register 1, and Table 19-2 Serial Interface Channel 2 Operating Mode Settings.
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4.2.4 P30 to P37 (Port 3) P30 to P37 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as timer input/output, clock output, and buzzer output. The following operating modes can be specified in 1-bit units. (1) Port mode P30 to P37 function as an 8-bit I/O port. They can be specified as an input or output using in 1-bit units port mode register 3 (PM3). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P30 to P37 function as timer input/output, clock output, and buzzer output. (a) TI1 and TI2 These are pins for inputting the external count clock to the 8-bit timer/event counter. (b) TO0 to TO2 These are timer output pins. (c) PCL This is a clock output pin. (d) BUZ This is a buzzer output pin.
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4.2.5 P40 to P47 (Port 4) P40 to P47 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating modes can be specified in 8-bit units. (1) Port mode P40 to P47 function as an 8-bit I/O port. They can be specified as input or output in 8-bit units using the internal memory expansion mode register (MM). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P40 to P47 function as the lower address/data bus pins (AD0 to AD7) in external memory expansion mode. When these pins are used as an address/data bus, on-chip pull-up resistors are automatically disabled. 4.2.6 P50 to P57 (Port 5) P50 to P57 function as an 8-bit I/O port. Besides serving as I/O port pins, they also function as an address bus. P50 to P57 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P50 to P57 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 5 (PM5). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P50 to P57 function as the higher address bus pins (A8 to A15) in external memory expansion mode. When these pins are used as an address bus, on-chip pull-up resistors are automatically disabled. 4.2.7 P60 to P67 (Port 6) P60 to P67 function as an 8-bit I/O port. Besides serving as I/O port pins, they are also used for control in external memory expansion mode. P60 to P63 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P60 to P67 function as an 8-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 6 (PM6). P60 to P63 are N-ch open-drain outputs. In mask ROM products, on-chip pull-up resistors can be connected to these pins using a mask option. When P64 to P67 are used as input port pins, on-chip pull-up resistor can be connected using pull-up resistor option register L (PUOL). (2) Control mode P60 to P67 functions as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode. When pins are used as control signal outputs, the on-chip pull-up resistors are automatically disabled. Caution When an external wait is not used in external memory expansion mode, P66 can be used as an I/O port pin.
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4.2.8 P70 to P72 (Port 7) P70 to P72 function as a 3-bit I/O port. Besides serving as I/O port pins, they also function as serial interface data I/O and clock I/O. The following operating modes can be specified in 1-bit units. (1) Port mode P70 to P72 function as a 3-bit I/O port. They can be specified as input port or output in 1-bit units using port mode register 7 (PM7). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register L (PUOL). (2) Control mode P70 to P72 function as serial interface data I/O and clock I/O. (a) SI2, SO2 These are serial data I/O pins of the serial interface. (b) SCK2 This is a serial clock I/O pin of the serial interface. (c) RxD0, TxD0 These are serial interface serial data I/O pins of the asynchronous serial interface. (d) ASCK This is a serial clock I/O pin of the asynchronous serial interface. Caution When P70 to P72 are used as serial interface pins, the I/O and output latches must be set according to the function the user requires. For the setting, see to the operation mode setting list in Table 19-2 Serial Interface Channel 2. 4.2.9 P120 to P127 (Port 12) P120 to P127 function as an 8-bit I/O port. Besides serving as an I/O port pins, they also function as a real-time output port. The following operating modes can be specified in 1-bit units. (1) Port mode P120 to P127 function as an 8-bit I/O port. They can be specified as input or output port in 1-bit units using port mode register 12 (PM12). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register H (PUOH). (2) Control mode P120 to P127 function as a real-time output port (RTP0 to RTP7) that outputs data in synchronization with a trigger.
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4.2.10 P130 and P131 (Port 13) P130 and P131 function as a 2-bit I/O port. Besides serving as I/O port pins, they also function as D/A converter analog output. The following operating modes can be specified in 1-bit units. (1) Port mode P130 and P131 function as a 2-bit I/O port. They can be specified as input or output in 1-bit units using port mode register 13 (PM13). When they are used as input port pins, on-chip pull-up resistors can be connected to them using pull-up resistor option register H (PUOH). (2) Control mode P130 and P131 function as D/A converter analog outputs (ANO0 and ANO1). Caution When only one of the D/A converter channels is used with AVREF1 < VDD0, the other pins that are not used as analog outputs must be set as follows: * * Set the PM13x bit of port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS0. Clear the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. 4.2.11 AVREF0 This is the A/D converter reference voltage input pin. This pin also serves as an analog power supply pin. Supply power to this pin when the A/D converter is used. When the A/D converter is not used, use the same voltage that of the VDD0 or VSS0 pin. 4.2.12 AVREF1 This is the D/A converter reference voltage input pin. When the D/A converter is not used, use the same voltage that of the VDD0 pin. 4.2.13 AVSS This is the ground voltage pin of A/D converter and D/A converter. Always use the same voltage as that of the VSS0 pin even when the A/D converter or D/A converter is not used. 4.2.14 RESET This is the low-level active system reset input pin. 4.2.15 X1 and X2 These are crystal resonator connection pins for main system clock oscillation. For external clock supply, input a signal to X1 and its inverted signal to X2. 4.2.16 XT1 and XT2 These are crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input a signal to XT1 and its inverted signal to XT2. 4.2.17 VDD0, VDD1 VDD0 is the positive power supply pin for ports. VDD1 is the positive power supply pin for blocks other than port and analog blocks.
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4.2.18 VSS0, VSS1 VSS0 is the ground potential pin for ports. VSS1 is the ground potential pin for blocks other than port and analog blocks. 4.2.19 VPP (Flash memory version only) This is the high-voltage apply pin for flash memory programming mode setting and program write/verify. Connect this pin in either of the following ways. * Connect independently to a 10 k pull-down resistor. * By using a jumper on the board, connect directly to the dedicated flash programmer in the programming mode or to VSS0 in the normal operation mode. 4.2.20 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the PD780058Y Subseries at delivery. Connect it directly to VSS0 with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and VSS0 pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally. Connect the IC pin to VSS0 directly.
VSS0 IC
As short as possible
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4.3 I/O Circuits and Recommended Connection of Unused Pins
Table 4-1 shows the pin I/O circuit types and the recommended connection of unused pins. Refer to Figure 4-1 for the configuration of the I/O circuit of each type. Table 4-1. Pin I/O Circuit Types (1/2)
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 5-N 5-H I/O I/O Input: Independently connect to VDD0 via a resistor. Output: Leave open. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. 5-H 8-C 5-H 16 11-D 8-C 5-H 8-C 5-H 8-C 10-B Input I/O Connect to VDD0 Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. I/O Circuit Type 2 8-C I/O Input I/O Recommended Connection of Unused Pins Connect to VSS0. Input: Independently connect to VSS0 via a resistor. Output: Leave open.
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Table 4-1. Pin I/O Circuit Types (2/2)
Pin Name P60 to P63 (mask ROM version) P60 to P63 (flash memory version) P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P120/RTP0 to P127/RTP7 P130/ANO0, P131/ANO1 RESET XT2 AVREF0 AVREF1 AVSS IC (mask ROM version) VPP (flash memory version) 8-C 5-H 8-C 5-H 12-C 2 16 -- I/O Input -- Leave open. Connect to VDD0 or VSS0. Connect to VDD0. Connect to VSS0. Connect directly to VSS0. Independently connect 10 k pull-down resistor, or connect to VSS0 or VSS1 directly. Input: Independently connect to VSS0 via a resistor. Output: Leave open. -- I/O Circuit Type 13-J 13-K 5-H I/O I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VDD0 via a resistor. Output: Set 0 to the port and leave open at low level output. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open.
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Figure 4-1. Pin I/O Circuit List (1/2)
Type 2 Type 8-C
VDD0
Pull-up enable IN VDD0 Data Schmitt-triggered input with hysteresis characteristics P-ch
P-ch
IN/OUT Output disable N-ch VSS0
Type 5-H
VDD0
Type 10-B
VDD0
Pull-up enable VDD0 Data P-ch
P-ch
Pull-up enable VDD0 Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch VSS0
Output disable
N-ch VSS0
Input enable Type 5-N VDD0 Type 11-D Pull-up enable Data VDD0 P-ch VDD0 P-ch IN/OUT P-ch IN/OUT Output disable N-ch VSS0 Input enable Output disable Comparator + - N-ch P-ch VSS0
Pull-up enable VDD0 Data
P-ch
N-ch VSS0 VREF (threshold voltage)
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Figure 4-1. Pin I/O Circuit List (2/2)
Type 12-C VDD0 Type 13-K IN/OUT P-ch VDD0 P-ch IN/OUT Output disable Input enable P-ch Analog output voltage N-ch Type 16 Feedback cut-off IN/OUT Data Output disable VSS0 VDD0 RD P-ch XT1 Medium breakdown input buffer XT2 N-ch P-ch N-ch VSS0 RD Data Output disable VSS0 VDD0 P-ch N-ch
Pull-up enable Data
Medium breakdown input buffer
Type 13-J Mask option
VDD0
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CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces
Figures 5-1 to 5-6 show the memory maps. Figure 5-1. Memory Map (PD780053, 780053(A), 780053Y, 780053Y(A))
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH FA80H FA7FH 5FFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area Internal ROM 24,576 x 8 bits 0040H 003FH Vector table area 0000H 0000H Program area
Data memory space
External memory 39,552 x 8 bits Program memory space 6000H 5FFFH
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Figure 5-2. Memory Map (PD780054, 780054(A), 780054Y, 780054Y(A))
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH FA80H FA7FH 7FFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area Internal ROM 32,768 x 8 bits 0040H 003FH Vector table area 0000H 0000H Program area
Data memory space
External Memory 31,360 x 8 bits Program memory space 8000H 7FFFH
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Figure 5-3. Memory Map (PD780055, 780055(A), 780055Y, 780055Y(A))
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH FA80H FA7FH 9FFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area Internal ROM 40,960 x 8 bits 0040H 003FH Vector table area 0000H 0000H Program area
Data memory space
External memory 23,168 x 8 bits Program memory space A000H 9FFFH
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Figure 5-4. Memory Map (PD780056, 780056(A), 780056Y, 780056Y(A))
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH FA80H FA7FH BFFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area Internal ROM 49,152 x 8 bits 0040H 003FH Vector table area 0000H 0000H Program area
Data memory space
External memory 14,976 x 8 bits Program memory space C000H BFFFH
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Figure 5-5. Memory Map (PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A))
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH F800H F7FFH EFFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area Internal expansion RAM 1,024 x 8 bits F400H F3FFH Unusable F000H EFFFH Program memory space 0000H
Note
Program area
Data memory space
0800H 07FFH Program area 0080H 007FH CALLT table area
Internal ROM 61,440 x 8 bits
0040H 003FH Vector table area 0000H
Note
When the internal ROM size is 60 KB, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to 56 KB or less using the internal memory size switching register (IMS).
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Figure 5-6. Memory Map (PD78F0058, 78F0058Y)
FFFFH
FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
Internal high-speed RAM 1,024 x 8 bits
FB00H FAFFH Unusable FAE0H FADFH FAC0H FABFH F800H F7FFH EFFFH Internal buffer RAM 32 x 8 bits Unusable 1000H 0FFFH CALLF entry area Internal expansion RAM 1,024 x 8 bits F400H F3FFH Unusable F000H EFFFH Program memory space 0800H 07FFH Program area
Note
Program area
Data memory space
0080H 007FH CALLT table area
Flash memory 61,440 x 8 bits
0040H 003FH Vector table area
0000H
0000H
Note
When the flash memory size is 60 KB, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the flash memory size to 56 KB or less using the internal memory size switching register (IMS).
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5.1.1 Internal program memory space The PD780058 and 780058Y Subseries have various sizes of internal ROM or flash memory as shown below. The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC).
Internal ROM Part Number Type Mask ROM Capacity 24,576 x 8 bits 32,768 x 8 bits 40,960 x 8 bits 49,152 x 8 bits 61,440 x 8 bits Flash memory 61,440 x 8 bits
PD780053, 780053(A), 780053Y, 780053Y(A) PD780054, 780054(A), 780054Y, 780054Y(A) PD780055, 780055(A), 780055Y, 780055Y(A) PD780056, 780056(A), 780056Y, 780056Y(A) PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A) PD78F0058, 78F0058Y
The internal program memory is divided into the following three areas.
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(1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon RESET input interrupt request or generation are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 5-1. Vector Table
Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 003EH Interrupt Source RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0 INTCSI1 INTSER INTSR/INTCSI2 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD BRK
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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5.1.2 Internal data memory space The PD780058 and 780058Y Subseries incorporate the following RAMs. (1) Internal high-speed RAM High-speed memory of the following configuration is incorporated: 1,024 x 8 bits (FB00H to FEFFH) In this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated to the 32-byte area FEE0H to FEFFH. The internal high-speed RAM can also be used as a stack memory area. (2) Internal buffer RAM Buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. The internal buffer RAM is used to store transmit/receive data of serial interface channel 1 (in 3-wire serial I/O mode with automatic transmit/receive function). If the 3-wire serial I/O mode with automatic transmit/receive function is not used, the internal buffer RAM can also be used as normal RAM. (3) Internal expansion RAM (PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A), 78F0058, 78F0058Y only) Internal expansion RAM is allocated to the 1,024-byte area from F400H to F7FFH. 5.1.3 Special Function Register (SFR) area On-chip peripheral hardware special-function registers (SFRs) are allocated to the area FF00H to FFFFH. (See Table 5-2 Special-Function Register List in 5.2.3 Special Function Registers (SFRs)). Caution Do not access addresses where SFRs are not assigned. 5.1.4 External memory space The external memory space is accessible by setting the internal memory expansion mode register (MM). External memory space can store program, table data, etc. and allocate peripheral devices. 5.1.5 Data memory addressing The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is addressed by the program counter PC (for details, see 5.3 Instruction Address Addressing). To address the memory that is manipulated when an instruction is executed, the PD780058, 780058Y Subseries is provided with many addressing modes with a high operability. Especially at addresses corresponding to data memory area, particular addressing modes can be used in accordance with the functions of the special function registers (SFRs) and general-purpose registers. This area is between FB00H and FFFFH. The data memory space is the entire 64 KB space (0000H to FFFFH). Figures 5-7 to 5-12 show the data memory addressing modes. For details of each addressing, see 5.4 Operand Address Addressing.
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Figure 5-7. Data Memory Addressing (PD780053, 780053(A), 780053Y, 780053Y(A))
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable FA80H FA7FH Direct addressing Register indirect addressing Based addressing Based indexed addressing
External memory 39,552 x 8 bits
6000H 5FFFH Internal ROM 24,576 x 8 bits 0000H
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Figure 5-8. Data Memory Addressing (PD780054, 780054(A), 780054Y, 780054Y(A))
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable FA80H FA7FH Direct addressing Register indirect addressing Based addressing Based indexed addressing
External memory 31,360 x 8 bits
8000H 7FFFH Internal ROM 32,768 x 8 bits 0000H
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Figure 5-9. Data Memory Addressing (PD780055, 780055(A), 780055Y, 780055Y(A))
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable FA80H FA7FH Direct addressing Register indirect addressing Based addressing Based indexed addressing
External memory 23,168 x 8 bits
A000H 9FFFH Internal ROM 40,960 x 8 bits 0000H
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Figure 5-10. Data Memory Addressing (PD780056, 780056(A), 780056Y, 780056Y(A))
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable FA80H FA7FH Direct addressing Register indirect addressing Based addressing Based indexed addressing
External memory 14,976 x 8 bits
C000H BFFFH Internal ROM 49,152 x 8 bits 0000H
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Figure 5-11. Data Memory Addressing (PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A))
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable F800H F7FFH Internal expansion RAM 1,024 x 8 bits F400H F3FFH UnusableNote F000H EFFFH Internal ROM 61,440 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing Based indexed addressing
Note
When the internal ROM size is 60 KB, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM size to 56 KB or less using the internal memory size switching register (IMS).
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Figure 5-12. Data Memory Addressing (PD78F0058, 78F0058Y)
FFFFH
FF20H FF1FH FF00H FEFFH FEE0H FEDFH
Special function registers (SFRs) 256 x 8 bits
SFR addressing
General-purpose registers 32 x 8 bits Internal high-speed RAM 1,024 x 8 bits
Register addressing Short direct addressing
FE20H FE1FH FB00H FAFFH Unusable FAE0H FADFH Internal buffer RAM 32 x 8 bits FAC0H FABFH Unusable F800H F7FFH Internal expansion RAM 1,024 x 8 bits F400H F3FFH UnusableNote F000H EFFFH Flash memory 61,440 x 8 bits 0000H Direct addressing Register indirect addressing Based addressing Based indexed addressing
Note
When the flash memory size is 60 KB, the area F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the flash memory size to 56 KB or less using the internal memory size switching register (IMS).
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5.2 Processor Registers
The PD780058 and 780058Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 5-13. Program Counter Format
15 PC 0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI, and POP PSW instructions. RESET input sets the PSW to 02H. Figure 5-14. Program Status Word Format
7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY
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(a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When IE = 0, all interrupt requests except the non-maskable interrupt are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request is acknowledged, and set to 1 when the EI instruction is executed. (b) Zero flag (Z) When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. The 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored in these flags. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the vectored interrupt whose priority is specified by the priority specification flag registers (PR0L, PR0H, and PR1L) (see 21.3 (3) flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. Priority specification flag registers (PR0L, PR0H, and PR1L)) to be low is disabled. Whether the interrupt is actually acknowledged is controlled by the status of the interrupt enable
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(3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area. Figure 5-15. Stack Pointer Format
15 SP 0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 5-16 and 5-17. Caution Because RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution. Figure 5-16. Data to Be Saved to Stack Memory
Interrupt and BRK instruction SP SP SP _ 2 SP _ 2 SP _ 1 SP Register pair lower Register pair upper SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 PSW
PUSH rp instruction
CALL, CALLF, and CALLT instruction
Figure 5-17. Data to Be Reset from Stack Memory
RETI and RETB instruction
POP rp instruction
RET instruction
SP SP + 1 SP SP + 2
Register pair lower Register pair upper SP
SP SP + 1 SP + 2
PC7 to PC0 PC15 to PC8
SP SP + 1 SP + 2 SP SP + 3
PC7 to PC0 PC15 to PC8 PSW
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5.2.2 General registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank containing eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt requests for each bank. Figure 5-18. General-Purpose Register Configuration (a) Absolute name
16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEE0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-bit processing
(b) Function name
16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing
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5.2.3 Special-Function Registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. These registers are allocated in the FF00H to FFFFH area. Special-function registers can be manipulated like general-purpose registers, with operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special-function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified using an address. * 8-bit manipulation Describe the symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified using an address. * 16-bit manipulation Describe the symbol reserved by assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 5-2 gives a list of special-function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the addresses of the special function register. These symbols are reserved words in the RA78K0 and defined by header file sfrbit.h in the CC78K0, and can be used as the operands of instructions when the RA78K0, ID78K0, ID78K0-NS, and SM78K0 are used. * R/W Indicates whether the corresponding special-function register can be read or written. R/W: Read/write enabled R: W: Read only Write only
* Manipulatable bit units indicates the bit units (1, 8, or 16 bits) in which the register can be manipulated. -- indicates that the register cannot be manipulated in the indicated bit units. * After reset Indicates each register status upon RESET input.
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Table 5-2. Special-Function Register List (1/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF07H FF0CH FF0DH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF22H FF23H FF25H FF26H FF27H FF2CH FF2DH FF30H FF31H FF34H FF36H Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 Capture/compare register 00 P0 P1 P2 P3 P4 P5 P6 P7 P12 P13 CR00 R/W -- 8 Bits -- 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- 00H 0000H Undefined 00H Undefined 00H After Reset
Capture/compare register 01
CR01
--
--
16-bit timer register
TM0
R
--
--
Compare register 10 Compare register 20 8-bit timer register 1 8-bit timer register 2 Serial I/O shift register 0 Serial I/O shift register 1 A/D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 Port mode register 6 Port mode register 7 Port mode register 12 Port mode register 13 Real-time output buffer register L Real-time output buffer register H Real-time output port mode register Real-time output port control register
CR10 CR20 TMS TM1 TM2 SIO0 SIO1 ADCR PM0 PM1 PM2 PM3 PM5 PM6 PM7 PM12 PM13 RTBL RTBH RTPM RTPC
R/W
-- --
Undefined
R
-- --
R/W
-- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Undefined
R R/W
-- -- --
FFH
00H
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Table 5-2. Special-Function Register List (2/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF38H FF39H FF3AH FF3BH FF40H FF41H FF42H FF43H FF47H FF48H FF49H FF4AH FF4CH FF4EH FF4FH FF60H FF61H FF62H FF63H FF68H FF69H FF6AH FF6BH FF70H FF71H FF72H FF73H FF74H Correction address register 0Note Correction address register 1Note CORAD0 R/W -- 8 Bits -- 16 Bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FFH Undefined 00H 04H 00H 88H 00H 00H 0000H After Reset
CORAD1
-- -- -- -- -- -- -- R RW -- W R R/W -- -- -- --
--
Timer clock select register 0 Timer clock select register 1 Timer clock select register 2 Timer clock select register 3 Sampling clock select register 16-bit timer mode control register 8-bit timer mode control register 1 Watch timer mode control register Capture/compare control register 0 16-bit timer output control register 8-bit timer output control register Serial operating mode register 0 Serial bus interface control register Slave address register Interrupt timing specify register Serial operating mode register 1 Automatic data transmit/receive control register Automatic data transmit/receive address pointer Automatic data transmit/receive interval specify register Asynchronous serial interface mode register Asynchronous serial interface status register Serial operating mode register 2 Baud rate generator control register Transmit shift register Receive buffer register
TCL0 TCL1 TCL2 TCL3 SCS TMC0 TMC1 TMC2 CRC0 TOC0 TOC1 CSIM0 SBIC SVA SINT CSIM1 ADTC ADTP ADTI ASIM ASIS CSIM2 BRGC TXS RXB SIPS ADM ADIS CORCN DACS0 DACS1 DAM SIO2
FF75H FF80H FF84H FF8AH FF90H FF91H FF98H
Serial interface pin select register A/D converter mode register A/D converter input select register Correction control registerNote D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register

-- -- -- -- -- -- --
00H 01H 00H
Note
This register is provided only in the PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A), 78F0058, and 78F0058Y.
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Table 5-2. Special-Function Register List (3/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FFD0H to FFDFH FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFECH FFEDH FFF0H FFF2H FFF3H FFF4H External access areaNote 1 IF0L IF0H IF1L MK0 MK0L MK0H MK1L PR0 PR0L PR0H PR1L INTM0 INTM1 IMS OSMS PUOH IXS W R/W W R/W R/W -- -- -- -- -- -- 8 Bits -- -- -- -- -- -- -- 0AH
Note 2
After Reset
16 Bits -- Undefined
Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority order specification flag register 0L Priority order specification flag register 0H Priority order specification flag register 1L External interrupt mode register 0 External interrupt mode register 1 Internal memory size switching register Oscillation mode select register Pull-up resistor option register H Internal expansion RAM size switching registerNote 3 Key return mode register Pull-up resistor option register L Memory expansion mode register Watchdog timer mode register Oscillation stabilization time select register Processor clock control register
IF0
00H
-- FFH
--
00H
00H
FFF6H FFF7H FFF8H FFF9H FFFAH FFFBH
KRM PUOL MM WDTM OSTS PCC
-- -- -- -- -- --
02H 00H 10H 00H 04H
Notes
1. The external access area cannot be accessed using SFR addressing. Access the area using direct addressing. 2. The value after reset depends on the product.
PD780053, 780053(A), 780053Y, 780053Y(A): C6H PD780054, 780054(A), 780054Y, 780054Y(A): C8H PD780055, 780055(A), 780055Y, 780055Y(A): CAH PD780056, 780056(A), 780056Y, 780056Y(A): CCH PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A): CFH PD78F0058, 78F0058Y: CFH
3. This register is provided only in the PD780058, 780058B, 780058B(A), 780058BY, 780058BY(A), 78F0058, and 78F0058Y.
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5.3 Instruction Address Addressing
The instruction address is determined by the program counter (PC) contents. The contents of the PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 Instructions User's Manual (U12326E). 5.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In the relative addressing modes, execution branches in a relative range of -128 to +127 from the first address of the next instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction.
When S = 0, all bits of are 0. When S = 1, all bits of are 1.
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5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instructions can branch in the entire memory space. The CALLF !addr11 instruction branches to an area of addresses 0800H to 0FFFH. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions
7 CALL or BR Low Addr. High Addr.
0
15 PC
87
0
In the case of CALLF !addr11 instruction
76 fa10 to 8
4
3 CALLF
0
fa7 to 0
15 PC 0 0 0 0
11 10 1
87
0
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5.3.3 Table indirect addressing [Function] The table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H to 7FH, and can branch in the entire memory space. [Illustration]
7 Operation code 1
6 1
5 ta4 to 0
1
0 1
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (table) Low Addr.
0
Effective address + 1
High Addr.
15 PC
8
7
0
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5.3.4 Register addressing [Function] The register pair (AX) contents to be specified by an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A
0
7 X
0
15 PC
8
7
0
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5.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register area is automatically (illicitly) addressed. In the PD780058 and 780058Y Subseries instruction words, the following instructions employ implied addressing.
Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing Register A for multiplicand and AX register for product storage Register AX for dividend and quotient storage Register A for storage of numeric values which become decimal correction targets Register A for storage of digit data which undergoes digit rotation
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example, the A and AX registers are specified by implied addressing.
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5.4.2 Register addressing [Function] This addressing accesses a general-purpose register as an operand. The general-purpose register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specification code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified by 3 bits in the operation code. [Operand format]
Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL
`r' and `rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Description example] MOV A, C; when selecting C register as r Operation code 01100010 Register specification code INCW DE; when selecting DE register pair as rp Operation code 10000100 Register specification code
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5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format]
Identifier addr16 Description Label or 16-bit immediate data
[Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 10001110 00000000 11111110 [Illustration] OP code 00H FEH
7 Opcode addr16 (lower) addr16 (higher)
0
Memory
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5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H to FF1FH. An internal RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) to which short direct addressing is applied is a part of the entire SFR area. Ports frequently accessed by the program, and the compare registers and capture registers of timer/event counters are mapped to this area. These SFRs can be manipulated with a short byte length and few clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] on next page. [Operand format]
Identifier saddr saddrp Description Label or immediate data of FE20H to FF1FH Label or immediate data of FE20H to FF1FH (even address only)
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[Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 00010001 00110000 01010000 [Illustration]
7 Opcode saddr-offset 0
OP code 30H (saddr-offset) 50H (immediate data)
Short direct memory 15 Effective Address 1 1 1 1 1 1 1 87 0
When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1
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5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Description Special-function register name 16-bit manipulatable special-function register name (even address only)
[Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 11110110 00100000 [Illustration]
7 Opcode sfr-offset 0
OP code 20H (sfr-offset)
SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0
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5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specification code in an instruction code. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [DE], [HL] Description
[Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code [Illustration]
15 DE D 87 E Memory address specified by register pair DE 0
10000101
7 Contents of addressed memory are transferred. 7 A 0
Memory
0
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5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1). The addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [HL + byte] Description
[Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 10101110 00010000
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5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1). The addition is performed by extending the contents of the B or C register to 16 bits as a positive number. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier -- [HL + B], [HL + C] Description
[Description example] In the case of MOV A, [HL + B] Operation code 5.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing can be used to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Operation code 10110101 10101011
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6.1 Port Functions
The PD780058 and 780058Y Subseries incorporate two input ports and sixty-six I/O ports. Figure 6-1 shows the port types. Every port can be manipulated in 1-bit and 8-bit units and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins. Figure 6-1. Port Types
Port 5 Port 6 Port 7 Port 12 Port 13
P50
P00
P05 P07 P57 P60 P10
Port 0
P67 P70 P72 P120
P17 P20
Port 1 Port 2 Port 3 Port 4
P27 P30 P127 P130 P131 P37 P40
P47
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Table 6-1. Port Functions (PD780058 Subseries) (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07 P10 to P17 Input only Port 1 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 2 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 0 7-bit I/O port Function Input only Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0 SO0/SB1 SCK0
Port 3 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Port 4 8-bit I/O port Input/output can be specified i 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. The test input flag (KRIF) is set to 1 by falling edge detection. Port 5 8-bit I/O port LED can be driven directly. Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
AD0 to AD7
P50 to P57
A8 to A15
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Table 6-1. Port Functions (PD780058 Subseries) (2/2)
Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P120 to P127 Port 7 3-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 12 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistor can be connected by setting software. Port 13 2-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistor can be connected by setting software. If used as an input port, an on-chip pull-up resistor can be connected by setting software. RD WR WAIT ASTB SI2/RxD0 SO2/TxD0 SCK2/ASCK RTP0 to RTP7 Function Port 6 8-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain I/O port On-chip pull-up resistors can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. Alternate Function --
P130 and P131
ANO0, ANO1
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Table 6-2. Port Functions (PD780058Y Subseries) (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07 P10 to P17 Input only Port 1 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 2 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 0 7-bit I/O port Function Input only Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Port 3 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Port 4 8-bit I/O port Input/output can be specified in 8-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. The test input flag (KRIF) is set to 1 by falling edge detection.
AD0 to AD7
P50 to P57
Port 5 8-bit I/O port LEDs can be driven directly. Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software.
A8 to A15
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Table 6-2. Port Functions (PD780058Y Subseries) (2/2)
Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P120 to P127 Port 7 3-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, an on-chip pull-up resistor can be connected by setting software. Port 12 8-bit I/O port Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistor can be connected by setting software. Port 13 2-bit I/O port Input/output mode can be specified in 1-bit units. If used as an input port, on-chip pull-up resistor can be connected by setting software. If used as an input port, an on-chip pull-up resistor can be connected by setting software. RD WR WAIT ASTB SI2/RxD0 SO2/TxD0 SCK2/ASCK RTP0 to RTP7 Function Port 6 8-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain I/O port On-chip pull-up resistors can be specified by mask option. (Mask ROM version only). LEDs can be driven directly. Alternate Function --
P130 and P131
ANO0, ANO1
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6.2 Port Configuration
A port consists of the following hardware. Table 6-3. Port Configuration
Item Control register Configuration Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13) Pull-up resistor option register (PUOH, PUOL) Memory expansion mode register (MM)Note Key return mode register (KRM) Port Pull-up resistor Total: 68 (Input: 2, I/O: 66) * Mask ROM version Total: 66 (software specifiable: 62, mask option: 4) * Flash memory version Total: 62
Note 6.2.1 Port 0
MM specifies the input/output mode of port 4.
Port 0 is a 7-bit I/O port with an output latch. Pins P01 to P05 can be set to input or output mode in 1-bit units using port mode register 0 (PM0). Pins P00 and P07 are input-only ports. When pins P01 to P05 are used as input ports, an on-chip pull-up resistor can be connected to them in 6-bit units using pull-up resistor option register L (PUOL). Alternate functions include external interrupt request input, external count clock input to the timer and crystal connection for subsystem clock oscillation. RESET input sets port 0 to input mode. Figures 6-2 and 6-3 show block diagrams of port 0. Caution Because port 0 also serves as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1.
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Figure 6-2. Block Diagram of P00 and P07
RD
Internal bus
P00/INTP0/TI00, P07/XT1
RD: Port 0 read signal Figure 6-3. Block Diagram of P01 to P05
VDD0 WRPUO PUO0 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P01 to P05) P01/INTP1/TI01, P02/INTP2 to P05/INTP5
WRPM PM01 to PM05
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 0 read signal Port 0 write signal
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6.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units using port mode register 1 (PM1). When pins P10 to P17 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). Alternate functions include A/D converter analog input. RESET input sets port 1 to input mode. Figure 6-4 shows a block diagram of port 1. Caution A pull-up resistor cannot be used for pins used as A/D converter analog inputs. Figure 6-4. Block Diagram of P10 to P17
VDD0 WRPUO PUO1 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P10 to P17) P10/ANI0 to P17/ANI7
WRPM PM10 to PM17
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 1 read signal Port 1 write signal
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6.2.3 Port 2 (PD780058 Subseries) Port 2 is an 8-bit I/O port with an output latch. Pins P20 to P27 can be set to input or output mode in 1-bit units using port mode register 2 (PM2). When pins P20 to P27 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output. RESET input sets port 2 to input mode. Figures 6-5 and 6-6 show a block diagram of port 2. Cautions 1. When used as serial interface pins, set input/output and the output latch according to the function. For the setting method, see Figure 16-4 Format of Serial Operating Mode Register 0, Figure 18-3 Format of Serial Operating Mode Register 1, and Table 19-2 Serial Interface Channel 2 Operating Mode Settings. 2. When reading the pin state in SBI mode, set the PM2n bit of PM2 to 1 (n = 5, 6) (See the description of (10) Judging busy state of slave in section 16.4.3 SBI mode operation). Figure 6-5. Block Diagram of P20, P21, and P23 to P26
VDD0 WRPUO PUO2 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P20, P21, P23 to P26)
P20/SI1, P21/SO1, P23/STB/TxD1, P24/BUSY/RxD1, P25/SI0/SB0, P26/SO0/SB1
WRPM PM20, PM21 PM23 to PM26
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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Figure 6-6. Block Diagram of P22 and P27
VDD0 WRPUO PUO2 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P22, P27) P22/SCK1, P27/SCK0
WRPM PM22, PM27
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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6.2.4 Port 2 (PD780058Y Subseries) Port 2 is an 8-bit I/O port with an output latch. Pins P20 to P27 can be set to input or output mode in 1-bit units using port mode register 2 (PM2). When pins P20 to P27 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output. RESET input sets port 2 to input mode. Figures 6-7 and 6-8 show a block diagram of port 2. Caution When used as serial interface pins, set input/output and the output latch according to the function. For the setting method, see Figure 17-4 Format of Serial Operating Mode Register 0, Figure 18-3 Format of Serial Operating Mode Register 1, and Table 19-2 Serial Interface Channel 2 Operating Mode Settings. Figure 6-7. Block Diagram of P20, P21, and P23 to P26
VDD0 WRPUO PUO2 RD
P-ch
Selector
Internal bus
WRPORT Output latch
(P20, P21, P23 to P26)
WRPM PM20, PM21 PM23 to PM26
P20/SI1, P21/SO1, P23/STB/TxD1, P24/BUSY/RxD1, P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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Figure 6-8. Block Diagram of P22 and P27
VDD0 WRPUO PUO2 RD
P-ch
Selector Internal bus WRPORT Output latch (P22 and P27) P22/SCK1, P27/SCK0/SCL
WRPM PM22, PM27
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
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6.2.5 Port 3 Port 3 is an 8-bit I/O port with an output latch. Pins P30 to P37 can be set to input or output mode in 1-bit units using port mode register 3 (PM3). When pins P30 to P37 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). Alternate functions include timer I/O, clock output and buzzer output. RESET input sets port 3 to input mode. Figure 6-9 shows a block diagram of port 3. Figure 6-9. Block Diagram of P30 to P37
VDD0 WRPUO PUO3 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P30 to P37)
WRPM PM30 to PM37
P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 3 read signal Port 3 write signal
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6.2.6 Port 4 Port 4 is an 8-bit I/O port with an output latch. Pins P40 to P47 can be set to input or output mode in 8-bit units using the memory expansion mode register (MM). When pins P40 to P47 are used as an input port, an on-chip pullup resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). The test input flag (KRIF) can be set to 1 by detecting a falling edge. Alternate functions include an address/data bus function in external memory expansion mode. RESET input sets port 4 to input mode. Figures 6-10 and 6-11 show a block diagram of port 4 and of the falling edge detector, respectively. Figure 6-10. Block Diagram of P40 to P47
VDD0 WRPUO PUO4 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P40 to P47) P40/AD0 to P47/AD7
WRMM MM
PUO: Pull-up resistor option register MM: RD: WR: Memory expansion mode register Port 4 read signal Port 4 write signal Figure 6-11. Block Diagram of Falling Edge Detector
P40 P41 P42 P43 P44 P45 P46 P47 KRMK Standby release signal Falling edge detector KRIF set signal
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6.2.7 Port 5 Port 5 is an 8-bit I/O port with an output latch. Pins P50 to P57 can be set to input or output mode in 1-bit units using the port mode register 5 (PM5). When pins P50 to P57 are used as an input port, an on-chip pull-up resistor can be connected to them in 8-bit units using pull-up resistor option register L (PUOL). Port 5 can drive LEDs directly. Alternate functions include an address bus function in external memory expansion mode. RESET input sets port 5 to input mode. Figure 6-12 shows a block diagram of port 5. Figure 6-12. Block Diagram of P50 to P57
VDD0 WRPUO PUO5 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P50 to P57) P50/A8 to P57/A15
WRPM PM50 to PM57
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 5 read signal Port 5 write signal
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6.2.8 Port 6 Port 6 is an 8-bit I/O port with an output latch. Pins P60 to P67 can be set to input or output mode in 1-bit units using port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions differ depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or flash memory model is used. Table 6-4. Pull-up Resistor of Port 6
Higher 4 Bits (P64 to P67 Pins) Mask ROM version Flash memory version On-chip pull-up resistor can be connected in 4-bit units by PUO6 Lower 4 Bits (P60 to P63 Pins) Pull-up resistor can be connected in 1-bit units by mask option Pull-up resistor is not connected
PUO6: Bit 6 of pull-up resistor option register L (PUOL) Pins P60 to P63 can drive LEDs directly. Alternate functions include a control signal output function in external memory expansion mode. RESET input sets port 6 to input mode. Figures 6-13 and 6-14 show block diagrams of port 6. Cautions 1. When an external wait is not used in external memory expansion mode, P66 can be used as an I/O port. 2. The value of the low-level input leakage current flowing to the P60 to P63 pins differ depending on the following conditions: [Mask ROM version] * When pull-up resistor is connected: Always -3 A (MAX.) * When pull-up resistor is not connected * * For duration of 1.5 clocks (no wait)Note when instruction such as MOV instruction to read port 6 (P6) and port mode register 6 (PM6) is executed: -200 A (MAX.) Other than above: -3 A (MAX.)
[Flash memory version] * For duration of 1.5 clocks (no wait)Note when instruction such as MOV instruction to read port 6 (P6) and port mode register 6 (PM6) is executed: * Other than above: Note At this time, on-chip pull-up resistors are enabled. -200 A (MAX.) -3 A (MAX.)
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Figure 6-13. Block Diagram of P60 to P63
VDD0 RD Mask option resistor Mask ROM versions only. Flash memory versions have no pull-up resistors.
Selector
Internal bus
WRPORT Output latch (P60 to P63) P60 to P63
WRPM PM60 to PM63
PM: RD: WR:
Port mode register Port 6 read signal Port 6 write signal Figure 6-14. Block Diagram of P64 to P67
VDD0
WRPUO PUO6 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P64 to P67) P64/RD, P65/WR, P66/WAIT, P67/ASTB
WRPM PM64 to PM67
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 6 read signal Port 6 write signal
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6.2.9 Port 7 This is a 3-bit I/O port with an output latch. Pins P70 to P72 can be set to input or output mode in 1-bit units using port mode register 7 (PM7). When pins P70 to P72 are used as an input port, an on-chip pull-up resistor can be connected in 3-bit units using pull-up resistor option register L (PUOL). Alternate functions include serial interface channel 2 data I/O and clock I/O. RESET input sets port 7 to input mode. Figures 6-15 and 6-16 show a block diagram of port 7. Caution When used as serial interface pins, set input/output and the output latch according to the function. For the setting method, see Table 19-2 Serial Interface Channel 2 Operating Mode Setting. Figure 6-15. Block Diagram of P70
VDD0 WRPUO PUO7 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P70) P70/SI2/RxD0
WRPM PM70
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 7 read signal Port 7 write signal
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Figure 6-16. Block Diagram of P71 and P72
VDD0 WRPUO PUO7 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P71 and P72) P71/SO2/TxD0, P72/SCK2/ASCK
WRPM PM71, PM72
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 7 read signal Port 7 write signal
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6.2.10 Port 12 This is an 8-bit I/O port with an output latch. Pins P120 to P127 can be set to input or output mode in 1-bit units using port mode register 12 (PM12). When pins P120 to P127 are used as an input port, an on-chip pull-up resistor can be connected in 8-bit units using pull-up resistor option register H (PUOH). These pins have an alternate function, serving as real-time outputs. RESET input sets port 12 to input mode. Figure 6-17 shows a block diagram of port 12. Figure 6-17. Block Diagram of P120 to P127
VDD0 WRPUO PUO12 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P120 to P127) P120/RTP0 to P127/RTP7
WRPM PM120 to PM127
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 12 read signal Port 12 write signal
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6.2.11 Port 13 This is a 2-bit I/O port with an output latch. Pins P130 and P131 can be set to input mode/output mode in 1-bit units using port mode register 13 (PM13). When pins P130 and P131 are used as an input port, an on-chip pull-up resistor can be connected in 2-bits using pull-up resistor option register H (PUOH). These pins have an alternate function, serving as D/A converter analog outputs. RESET input sets port 13 to input mode. Figure 6-18 shows a block diagram of port 13. Caution When only one of the D/A converter channels is used with AVREF1 < VDD0, the other pins that are not used as analog outputs must be set as follows: * * Set the PM13 bit of port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS0. Clear the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. Figure 6-18. Block Diagram of P130 and P131
VDD0 WRPUO PUO13 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P130 and P131) P130/ANO0, P131/ANO1
WRPM PM130, PM131
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 13 read signal Port 13 write signal
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6.3 Port Function Control Registers
The following four types of registers control the ports. * Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) * Pull-up resistor option registers (PUOH, PUOL) * Memory expansion mode register (MM) * Key return mode register (KRM) (1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) These registers are used to set port input/output in 1-bit units. PM0 to PM3, PM5 to PM7, PM12, and PM13 are independently set with a 1-bit or 8-bit memory manipulation instruction RESET input sets these registers to FFH. When port pins are used as the alternate-function pins, set the port mode register and output latch according to Table 6-5. Cautions 1. Pins P00 and P07 are input-only pins. 2. As port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. The memory expansion mode register (MM) specifies the input/output mode of pins P40 to P47.
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Table 6-5. Port Mode Register and Output Latch Settings When Using Alternate Functions
Pin Name Alternate Function Name P00 INTP0 TI00 P01 INTP1 TI01 P02 to P05 P07Note 1 P10 to P17Note 1 P30 to P32 P33, P34 P35 P36 P40 to P47 P50 to P57 P64 P65 P66 P67 P120 to P127 P130, P131Note 1 INTP2 to INTP5 XT1 ANI0 to ANI7 TO0 to TO2 TI1, TI2 PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB RTP0 to RTP7 ANO0, ANO1 I/O Input Input Input Input Input Input Input Output Input Output Output I/O Output Output Output Input Output Output Output 0 1 1 (fixed) 1 (fixed) 1 1 1 1 (fixed) 1 0 1 0 0 xNote 2 xNote 2 xNote 2 xNote 2 xNote 2 xNote 2 Desired value x None None x x x None x 0 x 0 0 PMxx Pxx
Notes
1. If these ports are read out when these pins are used in the alternate-function mode, undefined values are read. 2. When the P40 to P47 pins, P50 to P57 pins, and P64 to P67 pins are used for alternate functions, set the function by the memory extension mode register (MM).
Cautions 1. When not using an external wait in the external memory extension mode, the P66 pin can be used as an I/O port. 2. When port 2 and port 7 are used for the serial interface, input/output and the output latch must be set according to the function. For the setting methods, see Figure 16-4 Format of Serial Operation Mode Register 0, Figure 17-4 Interface Channel 2 Operating Mode Settings. Remark x: PMxx: Pxx: don't care Port mode register Port output latch Format of Serial Operation Mode Register 0, Figure 18-3 Format of Serial Operation Mode Register 1, and Table 19-2 Serial
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Figure 6-19. Port Mode Register Format
Symbol PM0
7 1
6 1
5
4
3
2
1
0 1
Address FF20H
After reset FFH
R/W R/W
PM05 PM04 PM03 PM02 PM01
PM1
PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
FF21H
FFH
R/W
PM2
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FF22H
FFH
R/W
PM3
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
FF23H
FFH
R/W
PM5
PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50
FF25H
FFH
R/W
PM6
PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60
FF26H
FFH
R/W
PM7
1
1
1
1
1
PM72 PM71 PM70
FF27H
FFH
R/W
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
FF2CH
FFH
R/W
PM13
1
1
1
1
1
1
PM131 PM130
FF2DH
FFH
R/W
PMmn 0 1
Pmn pin I/O mode selection (m = 0 to 3, 5 to 7, 12, 13 : n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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(2) Pull-up resistor option registers (PUOH, PUOL) These registers are used to set whether to use an on-chip pull-up resistor at each port or not. A pull-up resistor is internally used at bits set to the input mode in a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up resistors can be used for bits set to the output mode or bits used as an analog input pin, irrespective of the PUOH or PUOL setting. PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Cautions 1. Pins P00 and P07 do not incorporate a pull-up resistor. 2. When ports 1, 4, 5, and pins P64 to P67 are used as alternate-function pins, an on-chip pull-up resistor cannot be used even if the PUOm bit of PUOH, PUOL (m = 1, 4 to 6) is set to 1. 3. Pins P60 to P63 can be connected to pull-up resistors by a mask option only for mask ROM versions. Figure 6-20. Format of Pull-up Resistor Option Register
After reset 00H
Symbol PUOH
7 0 <7>
6 0 <6>
<5>
<4>
3 0 <3>
2 0 <2>
1 0 <1>
0 0 <0>
Address FFF3H
R/W R/W
PUO13 PUO12 <5> <4>
PUOL
PUO7 PUO6 PUO5 PUO4 PUO3 PUO2 PUO1 PUO0
FFF7H
00H
R/W
PUOm 0 1
Pm internal pull-up resistor selection (m = 0 to 7, 12, 13) Internal pull-up resistor not used Internal pull-up resistor used
Caution
Be sure to clear bits 0 to 3, 6, and 7 of PUOH to 0.
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(3) Memory expansion mode register (MM) This register is used to set the input/output mode of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 6-21. Format of Memory Expansion Mode Register
After reset 10H
Symbol MM
7 0
6 0
5 PW1
4 PW0
3 0
2 MM2
1 MM1
0 MM0
Address FFF8H
R/W R/W
MM2 MM1
MM0
Single-chip/memory expansion mode selection Single-chip mode
P40 to P47, P50 to P57, P64 to P67 pin state P40 to P47 P50 to P53 Port Input mode Output Port mode P54, P55 P56, P57 P64 to P67
0 0 0
0 0 1
0 1 1
Memory expansion mode
256-byte mode 4 KB mode 16 KB mode Full Note address mode
AD0 to AD7 Port mode A8 to A11 Port mode
P64 = RD P65 = WR P66 = WAIT A12, A13 Port mode P67 = ASTB A14, A15
1 1 1
0 0 1
0 1 1
Other than above
Setting prohibited
PW1 PW0 0 0 1 1 0 1 0 1 No wait
Wait control
Wait (one wait state inserted) Setting prohibited Wait control by external wait pin
Note
The full address mode allows external expansion for all areas of the 64 KB address space, except the internal ROM, RAM, SFR, and use-prohibited areas.
Remarks 1. Pins P60 to P63 enter the port mode in both the single-chip and memory expansion mode. 2. Besides setting port 4 input/output mode, MM also sets the wait count and external expansion area.
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(4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 6-22. Format of Key Return Mode Register
After reset 02H
Symbol KRM
7 0
6 0
5 0
4 0
3 0
2 0
<1>
<0>
Address FFF6H
R/W R/W
KRMK KRIF
KRIF 0 1
Key return signal detection flag Not detected Detected (falling edge detection of port 4)
KRMK 0 1
Standby mode control by key return signal Standby mode release enabled Standby mode release disabled
Caution When falling edge detection of port 4 is used, KRIF should be cleared to 0 (it is not cleared to 0 automatically).
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6.4 Port Operations
Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 6.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 6.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is off, the pin status does not change. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
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6.5 Selection of Mask Option
The following mask option is provided in mask ROM versions. The flash memory versions have no mask options. Table 6-6. Comparison Between Mask ROM Version and Flash Memory Version
Pin Name Mask option for pins P60 to P63 Mask ROM Version On-chip pull-up resistors can be selected in 1-bit units. Flash Memory Version No on-chip pull-up resistor
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7.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock oscillator is not used, not using the internal feedback resistor can be set by the processor clock control register (PCC). This enables a decrease in the power consumption in STOP mode.
7.2 Clock Generator Configuration
The clock generator consists of the following hardware. Table 7-1. Clock Generator Configuration
Item Control registers Configuration Processor clock control register (PCC) Oscillation mode select register (OSMS) Main system clock oscillator Subsystem clock oscillator
Oscillator
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Figure 7-1. Clock Generator Block Diagram
FRC
XT1/P07 XT2
Subsystem clock oscillator Main system clock oscillator
fXT Prescaler
Watch timer, clock output function Clock to peripheral hardware
Selector
X1 X2
fX Scaler
1/2 Prescaler fXX fXX 4 fXX 23 2 fXX 22 fXX 2 fXT 2
Selector
fX 2
Standby controller
Wait controller
CPU clock (fCPU)
3 STOP MCS Oscillation mode select register Internal bus
To INTP0 sampling clock
MCC FRC CLS CSS PCC2 PCC1 PCC0
Processor clock control register
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7.3 Clock Generator Control Registers
The clock generator is controlled by the following two registers. * Processor clock control register (PCC) * Oscillation mode select register (OSMS) (1) Processor clock control register (PCC) PCC sets the CPU clock selection, division ratio, main system clock oscillator operation/stop and whether to use the subsystem clock oscillator internal feedback resistorNote. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 04H. Note The feedback resistor is necessary for adjusting the bias point of an oscillated waveform to the middle level of the supply voltage. Only when the subsystem clock is not used, the current consumption in the STOP mode can be further reduced by setting bit 6 (FRC) of PCC to 1. Figure 7-2. Subsystem Clock Feedback Resistor
FRC P-ch Feedback resistor
XT1
XT2
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Figure 7-3. Format of Processor Clock Control Register
Symbol PCC <7> MCC <6> FRC <5> CLS <4> CSS 3 0 2 1 0 Address FFFBH After reset 04H R/W R/WNote 1
PCC2 PCC1 PCC0
R/W
CSS PCC2 PCC1 PCC0
CPU cIock selection (fCPU) MCS = 1 MCS = 0 fX/2 fX/22 fX/23 fX/24 fX/25
2 3
0
0 0 0 0 1
0 0 1 1 0 0 0 1 1 0
0 1 0 1 0 0 1 0 1 0
fXX fXX/2 fXX/2 fXX/2
2 3
fX fX/2 fX/2 fX/2
fXX/24 fXT/2
fX/24
1
0 0 0 0 1
Other than above
Setting prohibited
R
CLS 0 1 Main system clock Subsystem clock
CPU clock status
R/W
FRC 0 1
Subsystem clock feedback resistor selection Internal feedback resistor used Internal feedback resistor not used
Note 2
R/W
MCC 0 1 Oscillation possible Oscillation stopped
Main system clock oscillation control
Note 3
Notes 1. Bit 5 is a read-only bit. 2. This bit can be set to 1 only when the subsystem clock is not used. 3. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. A STOP instruction should not be used. Caution Be sure to clear bit 3 to 0. Remarks 1. fXX: 2. fX: 3. fXT: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency
4. MCS: Bit 0 of oscillation mode select register (OSMS)
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The fastest instruction of the PD780058, 780058Y Subseries is executed in 2 CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in Table 72. Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s 12.8 s 122 s
fX fX/2 fX/22 fX/23 fX/24 fX/25 fXT/2
fX = 5.0 MHz, fXT = 32.768 kHz fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency
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(2) Oscillation mode select register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the divider is used as the main system clock, or the clock output via the divider is used as the main system clock. OSMS is set with an 8-bit memory manipulation instruction. RESET input clears OSMS to 00H. Figure 7-4. Format of Oscillation Mode Selection Register
After reset 00H
Symbol OSMS
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 MCS
Address FFF2H
R/W W
MCS 0 1
Main system clock divider control Divider used Divider not used
Cautions 1. Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts. As shown in Figure 7-5 below, writing data (including the same data as previously) to OSMS causes a main system clock cycle delay of up to 2/ fX during the write operation. Therefore, if this register is written during the operation, in peripheral hardware which operates on the main system clock, a temporary error occurs in the count clock cycle of timer, etc. In addition, because the oscillation mode is changed by this register, the clock for peripheral hardware as well as that for the CPU is switched. Figure 7-5. Main System Clock Waveform due to Writing to OSMS
Write to OSMS (MCS 0) Max. 2/fX fXX
Operating at fXX = fX/2 (MCS = 0)
Operating at fXX = fX/2 (MCS = 0)
2. When writing 1 to MCS, VDD must be 2.7 V or higher before the write operation. Remark fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency
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7.4 System Clock Oscillator
7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and the inverse signal to the X2 pin. Figure 7-6 shows an external circuit of the main system clock oscillator. Figure 7-6. External Circuit of Main System Clock Oscillator (a) Crystal and ceramic oscillation (b) External clock
X2
X2
VSS1
X1 IC Crystal or ceramic resonator
External clock
X1
Cautions 1. Do not execute the STOP instruction or set MCC (bit 7 of the processor clock control register (PCC)) to 1 if an external clock is used. Otherwise, the operation of the main system clock will be stopped and the X2 pin will be pulled up to VDD1. 2. When using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in Figures 7-6 and 7-7 to prevent any effects from wiring capacities. * * * * Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS1. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator.
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7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin. Figure 7-7 shows an external circuit of the subsystem clock oscillator. Figure 7-7. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation
IC 32.768 kHz VSS1 XT2 External Clock XT2
(b) External clock
XT1
XT1
PD74HCU04
Caution When using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken line area in Figures 7-6 and 7-7 to prevent any effects from wiring capacities. * Minimize the wiring length. * Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. * Set the potential of the grounding position of the oscillator capacitor to that of VSS1. Do not ground to any ground pattern where high current is present. * Do not fetch signals from the oscillator. Take special note of the fact that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption.
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7.4.3 Example of resonator with bad connection Figure 7-8 shows examples of resonators with bad connections. Figure 7-8. Examples of Resonator with Bad Connection (1/2) (a) Too long wiring (b) Crossed signal lines
PORTn (n = 0 to 7, 12, 13)
X2
X1
IC
X2
X1
IC
VSS1
VSS1
(c) Wiring near high fluctuating current
(d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
VDD
Pnm X2 X1 IC X2 X1 IC
High Current
A VSS1
B
C
High Current VSS1
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
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Figure 7-8. Examples of Resonator with Bad Connection (2/2) (e) Signals are fetched
X2
X1
IC
VSS1
Remark
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
Caution If XT2 and XT1 are wired in parallel, the cross-talk noise of X1 may increase with XT2, resulting in malfunction. To prevent this, it is recommended to wire XT2 and X1 so that they are not in parallel, and to connect the IC pin between XT2 and X1 directly to VSS1. 7.4.4 Divider The divider divides the main system clock oscillator output (fXX) and generates various clocks. 7.4.5 When not using subsystem clock If it is not necessary to use the subsystem clock for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1: Connect to VDD0 XT2: Leave open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To suppress the leakage current, disconnect the above internal feedback resistor by setting bit 6 (FRC) of the processor clock control register (PCC) to 1. In this case also, connect the XT1 and XT2 pins as described above.
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7.5 Clock Generator Operations
The clock generator generates the following clocks and controls the CPU operating mode including the standby mode. * Main system clock * Subsystem clock * CPU clock fCPU fXX fXT
* Clock to peripheral hardware The following clock generator functions and operations are determined by the processor clock control register (PCC) and the oscillation mode selection register (OSMS). (a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (12.8 s when operated at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while a low level is applied to the RESET pin. (b) With the main system clock selected, one of the six types of minimum instruction execution times (0.4 s, 0.8
s, 1.6 s, 3.2 s, 6.4 s, 12.8 s @ 5.0 MHz) can be selected by setting the PCC and OSMS registers.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. In a system where the subsystem clock is not used, the current consumption in the STOP mode can be further reduced by specifying with not to use the feedback resistor using bit 6 (FRC) of the PCC register. (d) The PCC register can be used to select the subsystem clock and to operate the system on a low current consumption (122 s when operated at 32.768 kHz). (e) With the subsystem clock selected, main system clock oscillation can be stopped by the PCC register. The HALT mode can be used, but not the STOP mode. (Subsystem clock oscillation cannot be stopped.) (f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to the 16-bit timer/event counter, watch timer, and clock output functions only. Thus, the 16-bit timer/event counter (when selecting watch timer output as the count clock when operating on the subsystem clock), the watch function, and the clock output function can also be continued in the standby state. However, since all other peripheral hardware operate on the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation).
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7.5.1 Main system clock operations When operating on the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) cleared to 0), the following operations are carried out by PCC settings. (a) Because the operation guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC register. (b) If bit 7 (MCC) of the PCC register is set to 1 when operating on the main system clock, the main system clock oscillation does not stop. When bit 4 (CSS) of PCC is set to 1 and the operation is subsequently switched to the subsystem clock (CLS = 1), the main system clock oscillation stops (see Figure 7-9). Figure 7-9. Main System Clock Stop Function (1/2) (a) Operation when MCC is set after setting CSS in case of main system clock operation
MCC
CSS CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
(b) Operation when MCC is set in case of main system clock operation
MCC CSS CLS L L Oscillation does not stop. Main system clock oscillation
Subsystem clock oscillation
CPU clock
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Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC in case of main system clock operation
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation CPU clock
7.5.2 Subsystem clock operations When operating on the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s when operating at 32.768 kHz) irrespective of bits 0 to 2 (PCC0 to PCC2) of the PCC register. (b) The watchdog timer stops counting. Caution Do not execute the STOP instruction while the subsystem clock is in operation.
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7.6 Changing System Clock and CPU Clock Settings
7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC; operation continues on the preswitchover clock for several instructions (see Table 7-3). Determination as to whether the system is operating on the main system clock or the subsystem clock is performed using bit 5 (CLS) of the PCC register.
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Set Values Before Switchover
CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 0
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Table 7-3. Maximum Time Required for CPU Clock Switchover
Set Values After Switchover MCS = 1 MCS = 0
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 1 x x x
16 instructions
16 instructions
16 instructions
16 instructions
fX/2fXT instruction (77 instructions)
fX/4fXT instruction (39 instructions)
0
1
8 instructions
8 instructions
8 instructions
8 instructions
fX/4fXT instruction (39 instructions)
fX/8fXT instruction (20 instructions)
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0
0
1
0
4 instructions
4 instructions
4 instructions
4 instructions
fX/8fXT instruction (20 instructions)
fX/16fXT instruction (10 instructions)
CLOCK GENERATOR
0
1
1
2 instructions
2 instructions
2 instructions
2 instructions
fX/16fXT instruction fX/32fXT instruction (10 instructions) (5 instructions)
1
0
0
1 instruction
1 instruction
1 instruction
1 instruction
fX/32fXT instruction fX/64fXT instruction (5 instructions) (3 instructions)
1
x
x
x
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
Remarks 1. 2. 3. Caution
One instruction is executed in the minimum instruction execution time with the pre-switchover CPU clock. MCS: Bit 0 of the oscillation mode selection register (OSMS) Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
Selection of the CPU clock cycle division ratio (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division ratio (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0).
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7.6.2 System clock and CPU clock switching procedure This section describes the procedure for switching between the system clock and the CPU clock. Figure 7-10. Switching Between System Clock and CPU Clock
VDD
RESET
Interrupt request signal
System clock CPU clock
fXX
fXX
fXT Subsystem clock operation
fXX High-speed operation
Minimum Maximum speed speed operation operation Wait (26.2 ms: 5.0 MHz) Internal reset operation
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation stabilization time (217/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 s when operated at 5.0 MHz). (2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds, the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and the maximum-speed operation is carried out. (3) Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) Upon detection of VDD voltage reset due to an interrupt request signal, bit 7 (MCC) of PCC is cleared to 0 and oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC and OSMS registers are rewritten and the maximum-speed operation is resumed. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER
8.1 16-Bit Timer/Event Counter Functions
The 16-bit timer/event counter (TM0) has the following functions. * Interval timer * PWM output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output PWM output and pulse width measurement can be used at the same time. (1) Interval timer TM0 generates interrupt requests at the preset time interval. Table 8-1. 16-Bit Timer/Event Counter Interval Times
Minimum Interval Time MCS = 1 2 x TI00 input cycle -- 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) MCS = 0 216 Maximum Interval Time MCS = 1 x TI00 input cycle -- 216 x 1/fX (13.1 ms) MCS = 0 MCS = 1 TI00 input edge cycle -- 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) Resolution MCS = 0
217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms)
1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns)
2 x watch timer output cycle
216 x watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency 2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz (2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of pulses of an externally input signal.
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(5) Square-wave output TM0 can output a square wave with any selected frequency. Table 8-2. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Time MCS = 1 2 x TI00 input cycle -- 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) MCS = 0 Maximum Pulse Time MCS = 1 216 x TI00 input cycle -- 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) MCS = 0 MCS = 1 TI00 input edge cycle -- 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) Resolution MCS = 0
1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns)
2 x watch timer output cycle
216 x watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX: Main system clock oscillation frequency 2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz (6) One-shot pulse output TM0 is able to output a one-shot pulse with any output pulse width.
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8.2 16-Bit Timer/Event Counter Configuration
The 16-bit timer/event counter consists of the following hardware. Table 8-3. 16-Bit Timer/Event Counter Configuration
Item Timer register Register Timer outputs Control registers 16 bits x 1 (TM0) Capture/compare register: 16 bits x 2 (CR00, CR01) 1 (TO0) Timer clock select register 0 (TCL0) 16-bit timer mode control register (TMC0) Capture/compare control register 0 (CRC0) 16-bit timer output control register (TOC0) Port mode register 3 (PM3) External interrupt mode register 0 (INTM0) Sampling clock select register (SCS)Note Configuration
Note
See Figure 21-1 Basic Configuration of Interrupt Function.
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Figure 8-1. Block Diagram of 16-Bit Timer/Event Counter
Internal bus Capture/compare control register 0 CRC02 CRC01 CRC00 INTP1
Selector
TI01/ P01/INTP1
16-bit capture/compare control register (CR00) Match PWM pulse output controller TMC01 to TMC03 16-bit timer register (TM0) Clear Match Clear circuit 3
INTTM00
Selector
INTTM3 2fXX fXX fXX/2 fXX/22 TI00/P00/ INTP0 Note 1
Note 2
16-bit timer/event counter output controller TMC01 to TMC03 2 INTTM01 INTP0 TO0/P30
3
TCL06 TCL05 TCL04 Timer clock select register 0 CRC02
16-bit capture/compare control register (CR01)
TMC03 TMC02 TMC01 OVF0
OSPT OSPETOC04 LVS0 LVR0 TOC01 TOE0 16-bit timer output control register
16-bit timer mode control register
Internal Bus
Notes 1. Edge detector 2. The configuration of the 16-bit timer/event counter output controller is shown in Figure 8-2.
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Figure 8-2. Block Diagram of 16-Bit Timer/Event Counter Output Controller
PWM pulse output controller
Level inversion
CRC02 INTTM01
INV S Q
Selector
CRC00 INTTM00
Selector
TO0/P30
TI00/P00/ INTP0
Edge detector
One-shot pulse output controller
R 3
2
ES11 ES10 External interrupt mode register 0
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 16-bit timer output control register
TMC03 TMC02 TMC01 16-bit timer mode control register
P30 output latch
PM30
Port mode register 3
Internal bus
Remark
The circuitry enclosed by the broken line is the output controller.
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(1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0. (a) When CR00 is used as a compare register The value set in CR00 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. It can also be used as the register that holds the interval time when TM0 is set to interval timer operation, and as the register that sets the pulse width when TM0 is set to PWM output operation. (b) When CR00 is used as a capture register It is possible to select the valid edge of the INTP0/TI00 pin or the INTP1/TI01 pin as the capture trigger. The INTP0/TI00 or INTP1/TI01 valid edge is set by external interrupt mode register 0 (INTM0). If CR00 is specified as a capture register and the capture trigger is specified to be the valid edge of the INTP0/TI00 pin, the situation is as shown in Table 8-4. On the other hand, when the capture trigger is specified to be the valid edge of the INTP1/TI01 pin, the situation is as shown in Table 8-5. Table 8-4. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
ES11 0 0 1 1 ES10 0 1 0 1 INTP0/TI00 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges No capture operation CR00 Capture Trigger Valid Edge Rising edge Falling edge
Table 8-5. INTP1/TI01 Pin Valid Edge and CR00 Capture Trigger Valid Edge
ES21 0 0 1 1 ES20 0 1 0 1 INTP1/TI01 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges Both rising and falling edges CR00 Capture Trigger Valid Edge Falling edge Rising edge
CR00 is set with a 16-bit memory manipulation instruction. RESET input makes CR00 undefined. Cautions 1. Set the data of PWM (14 bits) to the higher 14 bits of CR00. At this time, clear the lower 2 bits to 00. 2. Set CR00 to a value other than 0000H in the clear & start mode entered on a match between TM0 and CR00. However, in the free-running mode and in the clear mode using the valid edge of TI00, if CR00 is set to 0000H, an interrupt request (INTTM00) is generated following overflow (FFFFH). 3. If the new value of CR00 is less than the value of the 16-bit timer register (TM0), TM0 continues counting, overflows, and then starts counting again from 0. If the new value of CR00 is less than the old value, the timer must be restarted after changing the value of CR00.
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(2) Capture/compare register 01 (CR01) CR01 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register 0. (a) When CR01 is used as a compare register The value set in CR01 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM01) is generated if they match. (b) When CR01 is used as a capture register It is possible to select the valid edge of the INTP0/TI00 pin as the capture trigger. The INTP0/TI00 valid edge is set by external interrupt mode register 0 (INTM0). Table 8-6. INTP0/TI00 Pin Valid Edge and CR01 Capture Trigger Valid Edge
ES11 0 0 1 1 ES10 0 1 0 1 INTP0/TI00 Pin Valid Edge Falling edge Rising edge Setting prohibited Both rising and falling edges Both rising and falling edges CR01 Capture Trigger Valid Edge Falling edge Rising edge
CR01 is set with a 16-bit memory manipulation instruction. RESET input makes CR01 undefined. Caution Set CR01 to a value other than 0000H in the clear & start mode entered on a match between TM0 and CR00. However, in the free-running mode and in the clear mode using the valid edge of TI00, if CR01 is set to 0000H, an interrupt request (INTTM01) is generated following overflow (FFFFH). (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read with a 16-bit memory manipulation instruction. When TM0 is read, the capture/compare register (CR01) should first be set as a capture register. RESET input clears TM0 to 0000H. Caution As reading of the value of TM0 is performed via CR01, the previously set value of CR01 is lost.
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8.3 16-Bit Timer/Event Counter Control Registers
The following seven registers are used to control the 16-bit timer/event counter. * Timer clock select register 0 (TCL0) * 16-bit timer mode control register (TMC0) * Capture/compare control register 0 (CRC0) * 16-bit timer output control register (TOC0) * Port mode register 3 (PM3) * External interrupt mode register 0 (INTM0) * Sampling clock select register (SCS) (1) Timer clock select register 0 (TCL0) This register is used to set the count clock of the 16-bit timer register. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TCL0 to 00H. Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock of the 16-bit timer register.
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Figure 8-3. Format of Timer Clock Select Register 0
Symbol <7> 6 5 4 3 2 1 0 Address FF40H After reset 00H R/W R/W
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00
PCL output clock selection MCS = 1 MCS = 0
0 0 0 0 1 1 1 1 1
0 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
fXT (32.768 kHz) fXX fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2
2 3 4
fX fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2 3 4
(5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz)
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2
(2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz)
3 4 5
5
5
6
6 7
6 7
7 8
Other than above
Setting prohibited
TCL06 TCL05 TCL04
16-bit timer register count clock selection MCS = 1 MCS = 0
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 0 1
TI00 (valid edge specifiable) 2fXX fXX fXX/2 fXX/2
2
Setting prohibited fX fX/2 fX/2
2
fX fX/2 fX/2 fX/2
2 3
(5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz)
(5.0 MHz) (2.5 MHz) (1.25 MHz)
Watch timer output (INTTM 3) Setting prohibited
Other than above
CLOE 0 1 Output disabled Output enabled
PCL output control
Cautions 1. The TI00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and the sampling clock frequency is selected by the sampling clock selection register (SCS). 2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory manipulation instruction. 3. To read the count value when TI00 has been specified as the TM0 count clock, the value should be read from TM0, not from 16-bit capture/compare register 01 (CR01). 4. When rewriting TCL0 to other data, stop the timer operation beforehand.
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Remarks 1. fXX: 2. fX: 3. fXT:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency
4. TI00: 16-bit timer/event counter input pin 5. TM0: 16-bit timer register 6. MCS: Bit 0 of oscillation mode select register (OSMS) 7. Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC0 to 00H. Caution The 16-bit timer register starts operation at the moment TMC01 to TMC03 are set to values other than 0, 0, 0 (operation stop mode). Set TMC01 to TMC03 to 0, 0, 0 to stop the operation.
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Figure 8-4. Format of 16-Bit Timer Mode Control Register
Symbol TMC0 7 0 6 0 5 0 4 0 3 2 1 <0> Address FF48H After reset 00H R/W R/W
TMC03 TMC02 TMC01 OVF0
OVF0 0 1 Overflow not detected Overflow detected
16-bit timer register overflow detection
TMC03 TMC02 TMC01
Operating mode or clear mode selection Operation stopped (TM0 cleared to 0) PWM mode (free running) Free-running mode
TO0 output timing selection
Interrupt request generation
0
0
0
No change
Not generated
0
0
1
PWM pulse output
0
1
0
Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge
Generated on match between TM0 and CR00, and match between TM0 and CR01
0
1
1
1
0
0
Clear & start on TI00 valid edge
Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge
1
0
1
1
1
0
Clear & start on match between TM0 and CR00
Match between TM0 and CR00 or match between TM0 and CR01 Match between TM0 and CR00, match between TM0 and CR01 or TI00 valid edge
1
1
1
Cautions 1. Switch the clear mode and the TO0 output timing after stopping the timer operation (by clearing TMC01 to TMC03 to 0, 0, 0). 2. Set the valid edge of the TI00/INTP0 pin using external interrupt mode register 0 (INTM0) and select the sampling clock frequency using the sampling clock select register (SCS). 3. When using the PWM mode, set the PWM mode and then set data to CR00. 4. If clear & start mode entered on a match between TM0 and CR00 is selected, when the set value of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, the OVF0 flag is set to 1. Remark TO0: TI00: TM0: CR00: 16-bit timer/event counter output pin 16-bit timer/event counter input pin 16-bit timer register Compare register 00
CR01: Compare register 01
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(3) Capture/compare control register 0 (CRC0) This register controls the operation of capture/compare registers 00 and 01 (CR00 and CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 to 04H. Figure 8-5. Format of Capture/Compare Control Register 0
Symbol CRC0
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FF4CH
After reset 04H
R/W R/W
CRC02 CRC01 CRC00
CRC00 0 1
CR00 operating mode selection Operates as compare register Operates as capture register
CRC01 0 1
CR00 capture trigger selection Captures on valid edge of TI01 Captures on reverse phase of valid edge of TI00
CRC02 0 1
CR01 operating mode selection Operates as compare register Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC0. 2. When clear & start mode entered on a match between TM0 and CR00 is selected by the 16-bit timer mode control register (TMC0), CR00 should not be specified as a capture register.
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(4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output controller. It sets R-S type flipflop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and the output trigger for a one-shot pulse by software. TOC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC0 to 00H.
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Figure 8-6. Format of 16-Bit Timer Output Control Register
Symbol TOC0 7 0 <6> <5> 4 <3> <2> 1 <0> Address FF4EH After reset 00H R/W R/W
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOE0 0 1
16-bit timer/event counter output control Output disabled (port mode) Output enabled
TOC01
In PWM mode Active level selection
In other modes Timer output F/F control by match of CR00 and TM0
Inversion operation disabled Inversion operation enabled
0 1
Active high Active low
LVS0 LVR0
16-bit timer/event counter timer output F/F status setting No change Timer output F/F reset to 0 Timer output F/F set to 1 Setting prohibited
0 0 1 1
0 1 0 1
TOC04 Timer output F/F control by match of CR01 and TM0 0 1 Inversion operation disabled Inversion operation enabled
OSPE 0 1
One-shot pulse output control Continuous pulse output One-shot pulse output
OSPT Control of one-shot pulse output trigger by software 0 1 One-shot pulse trigger not used One-shot pulse trigger used
Cautions 1. Timer operation must be stopped before setting TOC0 (except OSPT). 2. If LVS0 and LVR0 are read after data is set, they will be 0. 3. OSPT is cleared automatically after data setting, and will therefore be 0 if read. 4. OSPT can be set only when OSPE = 1.
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(5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 8-7. Format of Port Mode Register 3
Symbol 7 6 5 4 3 2 1 0 Address FF23H After reset FFH R/W R/W
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin input/output mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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(6) External interrupt mode register 0 (INTM0) This register is used to set the valid edges of INTP0 to INTP2, TI00, and TI01. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 8-8. Format of External Interrupt Mode Register 0
Symbol 7 6 5 4 3 2 1 0 0 0 Address FFECH After reset 00H R/W R/W
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
ES11 0 0 1 1
ES10 0 1 0 1
INTP0/TI00 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES21 0 0 1 1
ES20 0 1 0 1
INTP1/TI01 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES31 0 0 1 1
ES30 0 1 0 1
INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
Caution When using the INTP0/TI00/P00 and INTP1/TI01/P01 pins as timer input pins (TI00 and TI01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI00 and TI01. When using the INTP0/TI00/P00 and INTP1/TI01/P01 pins as external interrupt input pins (INTP0 and INTP1), the valid edge of INTP0 and INTP1 may be set while 16-bit timer 0 is operating.
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(7) Sampling clock select registers (SCS) This register sets the clock used as the clock for sampling the valid edges input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is eliminated by the sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input clears SCS to 00H. Figure 8-9. Format of Sampling Clock Select Register
Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H After reset 00H R/W R/W
SCS1 SCS0
SCS1 SCS0
INTP0 sampling clock selection MCS = 1 MCS = 0
0 0 1 1
0 1 0 1
fXX/2 fXX/2 fXX/2 fXX/2
N 7 5 7 5 8 6
fX/2 (39.1 kHz) fX/2 (156.3 kHz) fX/2 (78.1 kHz)
6
fX/2 (19.5 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz)
7
6
Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are clocks supplied to peripheral hardware. The fXX/2N clock is stopped in HALT mode. Remarks 1. N: 2. fXX: 3. fX: Value set to bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0 to 4) Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
4. MCS: Bit 0 of oscillation mode select register (OSMS) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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8.4 16-Bit Timer/Event Counter Operations
8.4.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set to 16-bit capture/compare register 00 (CR00) beforehand as the interval. When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with the TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated. The count clock of the 16-bit timer/event counter can be selected using bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0). For the operation when the value of the compare register is changed during the timer/counter operation, see 8.6 (3) Operation after compare register change during timer count operation. Figure 8-10. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start on match TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 is set as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details.
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Figure 8-11. Interval Timer Configuration Diagram
16-bit capture/compare register 00 (CR00)
INTTM3 Selector 2fXX fXX fXX/2 fXX/2 TI00/P00/INTP0
2
INTTM00
16-bit timer register (TM0)
OVF0
Clear circuit
Figure 8-12. Interval Timer Operation Timings
t
Count clock
TM0 count value
0000
0001
N
0000 0001 Clear
N
0000 0001 Clear
N
Count start
CR00
N
N
N
N
INTTM00 Interrupt request acknowledge Interrupt request acknowledge TO0
Interval time
Interval time
Interval time
Remark
Interval time = (N + 1) x t : N = 0001H to FFFFH.
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Table 8-7. 16-Bit Timer/Event Counter Interval Times
TCL06 TCL05 TCL04 Minimum Interval Time MCS = 1 0 0 0 0 0 1 MCS = 0 Maximum Interval Time MCS = 1 216 MCS = 0 Resolution MCS = 1 MCS = 0
2 x TI00 input cycle Setting prohibited 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s)
x TI00 input cycle 216 x 1/fX (13.1 ms)
TI00 input edge cycle Setting prohibited 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s)
Setting prohibited 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms)
0
1
0
217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms)
0
1
1
1
0
0
1
1 Other than above
1
2 x watch timer output cycle Setting prohibited
216 x watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX: 2. MCS:
Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
3. TCL04 to TCL06: Bits 4 to 6 of timer clock select register (TCL0) 4. Values in parentheses apply to operation with fX = 5.0 MHz 8.4.2 PWM output operations Setting the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) as shown in Figure 8-13 allows operation as PWM output. Pulses with the duty rate determined by the value set to 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/ P30 pin. Set the active level width of the PWM pulse to the higher 14 bits of CR00. Select the active level using bit 1 (TOC01) of the 16-bit timer output control register (TOC0). This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 28/ and the sub-cycle determined by 214/ so that the time constant of the external LPF can be shortened. The count clock can be selected using bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0). PWM output enable/disable can be selected using bit 0 (TOE0) of TOC0. Cautions 1. PWM operation mode should be selected before setting CR00. 2. Be sure to clear bits 0 and 1 of CR00 to 0. 3. Do not select PWM operation mode for external clock input from the TI00/P00/INTP0 pin.
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Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 0 1 0
PWM mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 is set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0
x
x
x
x
x
0/1
1 TO0 output enabled Specifies active level
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with PWM output. See the description of the respective control registers for details. x: don't care
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By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. Capture/compare register 00 (CR00) value 216 VREF: External switching circuit reference voltage Figure 8-14. Example of D/A Converter Configuration with PWM Output
VAN = VREF x
PD780058, 780058Y
VREF PWM signal
TO0/P30
Switching circuit
Low-pass filter
Analog output (VAN)
Figure 8-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner. Figure 8-15. TV Tuner Application Circuit Example
+110 V
PD780058, 780058Y
22 k 47 k 100 pF TO0/P30 8.2 k 8.2 k VSS0 VSS0 GND 2SC 2352 0.22 F
PC574J
47 k
47 k
0.22 F
0.22 F
Electronic tuner
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8.4.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand to 16-bit capture/compare register 01 (CR01) and 16-bit capture/ compare register 00 (CR00), respectively. Figure 8-16. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0 0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 x 0 CR00 is set as compare register CR01 is set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0 0 0 1 0/1 0/1 1 1 TO0 output enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output disabled
Remark
x : don't care
Cautions 1. CR00 and CR01 should be set to values in the following range: 0000H CR01 < CR00n FFFFH 2. The cycle of the pulse generated through PPG output (CR00 setting value + 1) has a duty of (CR01 setting value + 1)/(CR00 setting value + 1).
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Figure 8-17. Configuration of PPG Output
16-bit timer capture/compare register 00 (CR00) INTTM3 2fXX fXX fXX/2 fXX/22 TI00/P00/INTP0 Noise eliminator
Selector
16-bit timer counter 0 (TM0)
Clear circuit
Output controller
TO0/P30
16-bit timer capture/compare register 01 (CR01)
Figure 8-18. PPG Output Operation Timing
t
Count clock TM0 count value 0000H 0001H Count start CR00 capture value CR01 capture value TO0 Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H
Clear
Remark
0000H < M < N FFFFH
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8.4.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin. (1) Pulse width measurement with free-running counter and one capture register When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-17), and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Any of three edge specifications can be selected--rising, falling, or both edges--by bits 2 and 3 (ES10 and ES11) of INTM0. For valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 8-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0/1 0 CR00 is set as compare register CR01 is set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 8-20. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
INTTM3 2fXX fXX fXX/2 fXX/2
2
Selector
16-bit timer register (TM0)
OVF0
TI00/P00/INTP00
16-bit capture/compare register 01 (CR01)
INTP0
Internal bus
Figure 8-21. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified)
t Count clock
TM0 count value
0000
0001
D0
D1
FFFF 0000
D2
D3
TI00 pin input
CR01 captured value
D0
D1
D2
D3
INTP0
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
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(2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal (INTP1) is set. Any of three edge specifications can be selected--rising, falling, or both edges--as the valid edges for the TI00/P00 pin and the TI01/P01 pin by bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and ES21) of INTM0, respectively. For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 8-22. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 0 1 CR00 is set as capture register Captured in CR00 on valid edge of TI01/P01 Pin CR01 is set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 8-23. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified)
t Count clock
TM0 count value
0000 0001
D0
D1
FFFF 0000
D2
D3
TI00 pin input
CR01 captured value
D0
D1
D2
D3
INTP0
TI01 pin input
CR00 captured value
D1
INTP1
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
(10000H - D1 + (D2 + 1)) x t
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(3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set. Also, on the reverse input edge to that of the capture operation into CR01, the value of TM0 is taken into 16bit capture/compare register 00 (CR00). Either of two edge specifications can be selected--rising or falling--as the valid edges for the TI00/P00 pin by bits 2 and 3 (ES10 and ES11) of INTM0. For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P00 is specified to be both the rising and falling edges, capture/ compare register 00 (CR00) cannot perform the capture operation. Figure 8-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0/1 0 Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 is set as capture register Captured in CR00 on reverse edge of valid edge of TI00/P00 Pin CR01 is set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details.
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Figure 8-25. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM0 count value
0000
0001
D0
D1
FFFF 0000
D2
D3
TI00 pin input
CR01 captured value
D0
D2
CR00 captured value
D1
D3
INTP0
OVF0
(D1 - D0) x t
(10000H - D1 + D2) x t
(D3 - D2) x t
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(4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24). The edge specification can be selected from two types, rising and falling edges by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0). In a valid edge detection, sampling is performed on the cycle selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Caution If the valid edge of TI00/P00 is specified to be both the rising and falling edges, 16-bit capture/ compare register 00 (CR00) cannot perform the capture operation. Figure 8-26. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 0 0/1 0 Clear & start on valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 1 1 1 CR00 is set as capture register Captured in CR00 on reverse edge to valid edge of TI00/P00 Pin CR01 is set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. Figure 8-27. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
t
Count clock TM0 count value TI00 pin input CR01 captured value CR00 captured value INTP0 D1 x t D0 D1 D2 0000 0001 D0 0000 0001 D1 D2 0000 0001
D2 x t
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8.4.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified by external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated. Set CR00 to a value other than 0000H (1-pulse count operation cannot be performed). The rising edge, falling edge or both edges can be selected using bits 2 and 3 (ES10 and ES11) of INTM0. Because operations are carried out only after the valid edge is detected twice by sampling at the interval selected by the sampling clock select register (SCS), noise with short pulse widths can be eliminated. Figure 8-28. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 is set as compare register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details.
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Figure 8-29. External Event Counter Configuration Diagram
16-bit capture/compare register 00 (CR00)
Clear
INTTM00
TI00 valid edge
16-bit timer register (TM0)
OVF0
INTP0
16-bit capture/compare register 01 (CR01)
Internal bus
Figure 8-30. External Event Counter Operation Timing (with Rising Edge Specified)
TI00 pin input
TM0 count value
0000
0001 0002 0003
0004
0005
N-1
N
0000 0001 0002 0003
CR00
N
INTTM00
Caution When reading the external event counter count value, TM0 should be read.
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8.4.6 Square-wave output operation The 16-bit timer/event counter outputs a square wave with any selected frequency at intervals specified by the count value set in advance to 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected frequency to be output. Figure 8-31. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 1 0/1 0 Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0/1 0/1 0 CR00 is set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 TOC0 0 0 0 0 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 output enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value No inversion of output on match of TM0 and CR01 One-shot pulse output disabled
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details.
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Figure 8-32. Square-Wave Output Operation Timing
Count clock TM0 count value CR00 INTTM0 TO0 pin output 0000 0001 0002 N N-1 N 0000 0001 0002 N-1 N 0000
Table 8-8. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Time MCS = 1 2 x TI00 input cycle -- 2 x 1/fX (400 ns) x 1/fX (800 ns) 22 23 x 1/fX (1.6 s) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 216 x 1/fX (13.1 ms) x 1/fX (26.2 ms) 217 218 x 1/fX (52.4 ms) MCS = 0 216 Maximum Pulse Time MCS = 1 x TI00 input cycle -- 216 x 1/fX (13.1 ms) 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) MCS = 0 MCS = 1 TI00 input edge cycle -- 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) Resolution MCS = 0
217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms)
24 x 1/fX (3.2 s)
219 x 1/fX (104.9 ms)
2 x watch timer output cycle
216 x watch timer output cycle
Watch timer output edge cycle
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz
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8.4.7 One-shot pulse output operation The 16-bit timer/event counter can be started in synchronization with a software trigger or external trigger (TI00/ P00 pin input) and output a one-shot pulse that ends on overflow of TM0. (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-31, and bit 6 (OSPT) of TOC0 is set to 1 by software, a one-shot pulse is output from the TO0/P30 pin. By setting OSPT to 1, the 16-bit timer/event counter is cleared and started, and output is activated by the count value (N) set beforehand to 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivatedNote by the count value (M) set beforehand in 16-bit capture/compare register 00 (CR00). TM0 continues to operate after a one-shot pulse is output. To stop TM0, TMC0 must be set to 00H. Note The case where N < M is described here. When N > M, the output becomes active with the CR00 register and inactive with the CR01 register. Cautions 1. When a one-shot pulse is output by a software trigger, fix the TI00/P00 pin to either the high or low level. 2. When outputting a one-shot pulse, do not set OSPT to 1. To output a one-shot pulse again, wait until the current one-shot pulse output is completed. Figure 8-33. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 0 1 0 0 Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 0/1 0 CR00 is set as compare register CR01 is set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 TOC0 0 0 1 1 0/1 LVR0 TOC01 TOE0 0/1 1 1 TO0 output enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output mode Set 1 in case of output
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. See the description of the respective control registers for details.
Caution Do not clear CR00 and CR01 to 0000H.
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Figure 8-34. One-Shot Pulse Output Operation Timing Using Software Trigger
Set 0CH to TMC0 (TM0 count start) Count clock TM0 count value CR01 set value CR00 set value OSPT INTTM01 INTTM00 TO0 pin output One-shot pulse 0000 N M 0001 N N+1 N M
0000
N-1 N M
N
M-1
M
M+1 N M
0000
Caution The 16-bit timer register starts operation at the moment TMC01 to TMC03 are set to values other than 0, 0, 0 (operation stop mode). Remark N198
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(2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger. Any of three edge specifications can be selected--rising, falling, or both edges--as the valid edges for the TI00/P00 pin by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0). When a valid edge is input to the TI00/P00 pin, the 16-bit timer/event counter is cleared and started, and output is activated by the count values (N) set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivatedNote by the count value (M) set beforehand in 16-bit capture/compare register 00 (CR00). Note The case where N < M is described here. When N > M, the output becomes active with the CR00 register and inactive with the CR01 register. Caution When outputting one-shot pulses, the external trigger is ignored if generated again. Figure 8-35. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger (a) 16-bit timer mode control register (TMC0)
TMC03 TMC02 TMC01 OVF0 TMC0 0 0 0 0 1 0 0 0 Clear & start on valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00 CRC0 0 0 0 0 0 0 0/1 0 CR00 is set as compare register CR01 is set as compare register
(c) 16-bit timer output control register (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 TOC0 0 0 1 1 0/1 0/1 1 1 TO0 output enabled Inversion of output on match of TM0 and CR00 Specified TO0 output F/F initial value Inversion of output on match of TM0 and CR01 One-shot pulse output mode
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. See the description of the respective control registers for details.
Caution Do not clear CR00 and CR01 to 0000H.
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Figure 8-36. One-Shot Pulse Output Operation Timing Using External Trigger (with Rising Edge Specified)
Set 08H to TMC0 (TM0 count start) Count clock TM0 count value CR01 set value CR00 set value TI00 pin input INTTM01 INTTM00 TO0 pin output 0000 0001 N M
0000
N
N+1 N M
N+2
M-2 M-1
M N M
M+1 M+2 M+3
N M
Caution The 16-bit timer register starts operation at the moment TMC01 to TMC03 are set to values other than 0, 0, 0 (operation stop mode). Remark N200
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8.5 16-Bit Timer/Event Counter Operating Cautions
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously to the count pulse. Figure 8-37. 16-Bit Timer Register Start Timing
Count pulse
TM0 count value
0000H
0001H
0002H
0003H
0004H
Timer start
(2) 16-bit compare register setting (when in the clear & start mode entered on a match between TM0 and CR00) Set 16-bit capture/compare register 00 (CR00) to the a value other than 0000H. Thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot be carried out. (3) Operation after compare register change during timer count operation If the value after the 16-bit capture/compare register (CR00) is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value after CR00 change (M) is smaller than that before change (N), it is necessary to reset and restart the timer after changing CR00. Figure 8-38. Timing After Change of Compare Register During Timer Count Operation
Count pulse
CR00
N
M
TM0 count value
X-1
X
FFFFH
0000H
0001H
0002H
Remark
N>X>M
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(4) Capture register data retention timing If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds the data without carrying out a capture operation. However, the interrupt request signal (PIF0) is set upon detection of the valid edge. Figure 8-39. Capture Register Data Retention Timing
Count pulse
TM0 count value
N
N+1
N+2
M
M+1
M+2
Edge input PIF0
Capture read signal
CR01 captured value
X
N+1
Capture operation ignored
(5) Valid edge setting When using the TI00/P00/INTP0 and TI01/P01/INTP1 pins as timer input pins (TI00 and TI01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI00 and TI01. The valid edge is set by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0). When using the TI00/P00/INTP0 and TI01/P01/ INTP1 pins as external interrupt input pins (INTP0 and INTP1), the valid edge of INTP0 and INTP1 may be set while 16-bit timer 0 is operating. (6) Re-trigger of one-shot pulse (a) One-shot pulse output using software When outputting a one-shot pulse, do not set OSPT to 1. To output a one-shot pulse again, wait until the current one-shot pulse output is completed. (b) One-shot pulse output using external trigger When outputting one-shot pulses, the external trigger is ignored if generated again. (c) One-shot pulse output function When using the software trigger for one-shot pulse output, fix the level of the TI00/P00/INTP0 and TI01/ P01/INTP1 pins to either the high or low level. Otherwise, the external trigger will remain valid even when the software trigger is used, and the timer will be cleared and started when the level of the TI00/P00/INTP0 or TI01/P01/INTP1 pin changes. In consequence, the pulse will be output unexpectedly.
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(7) Operation of OVF0 flag (a) OVF0 flag setting OFV0 flag is set to 1 in the following case. When one of clear & start mode on match between TM0 and CR00, clear & start mode on TI00 valid edge, or free-running mode is selected.
CR00 is set to FFFFH.
TM0 is counted up from FFFFH to 0000H. Figure 8-40. Operation Timing of OVF0 Flag
Count pulse
CR00
FFFFH
TM0
FFFEH
FFFFH
0000H
0001H
OVF0
INTTM00
(b) Clear OVF0 flag Even if the OVF0 flag is cleared before the next count clock is counted (before TM0 becomes 0001H) after TM0 has overflowed, the OVF0 flag is set again and the clear becomes invalid. (8) Conflict operation (a) If the read period and capture trigger input conflict If the read period and inputting a capture trigger conflict while 16-bit capture/compare registers 00 and 01 (CR00 and CR01) are used as capture registers, the registers do not perform a capture operation but hold data. However, the interrupt request flag (PIF0) is set when the valid edge is detected. (b) If the match timing of the write period and TM0 conflict When 16-bit capture/compare registers 00 and 01 (CR00, CR01) are used as capture registers, because match detection cannot be performed correctly if the match timing of the write period and 16-bit timer register 0 (TM0) conflict, do not write to CR00 and CR01 close to the match timing.
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(9) Timer operation (a) CR01 capture Even if 16-bit timer register 0 (TM0) is read, a capture to 16-bit capture/compare register 01 (CR01) is not performed. (b) Acknowledgement of TI00 and TI01 pins When the timer is stopped, input signals to the TI00 and TI01 pins are not acknowledged, regardless of the CPU operation. (10) Capture operation (a) If the valid edge of TI00 is specified for the count clock When the valid edge of TI00 is specified for the count clock, the capture register with TI00 specified as a trigger will not operate correctly. (b) If both rising and falling edges are selected as the valid edge of TI00. When both the rising and falling edges are selected as the valid edge of TI00, CR00 cannot perform a capture operation with TI00 specified as the capture trigger. (c) To use signal from TI00 as capture trigger For an accurate capture operation, a pulse longer than twice the width of the count clock selected by the sampling clock select register (SCS) is necessary. (11) Compare operation (a) When rewriting CR00 and CR01 during timer operation When rewriting 16-bit timer capture/compare registers 00 and 01 (CR00, CR01), if the value is close to or larger than the timer value, the match interrupt request generation or clear operation may not be performed correctly. (b) When CR00 and CR01 are set to compare mode When CR00 and CR01 are set to compare mode, they do not perform a capture operation even if a capture trigger is input. (12) Edge detection (a) When the TI00 or TI01 pin is high level immediately after a system reset When the TI00 or TI01 pin is high level immediately after a system reset, if the valid edge of the TI00 or TI01 pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/ counter 0 (TM0) is then enabled, the rising edge will be detected immediately. Care is therefore needed when the TI00 or TI01 pin is pulled up. However, when operation is enabled after being stopped, the rising or falling edge is not detected.
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9.1 8-Bit Timer/Event Counter Functions
For the 8-bit timer/event counter, two modes are available. One is a mode for the two 8-bit timer/event counter channels to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.1 8-bit timer/event counter mode The 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions. * Interval timer * External event counter * Square-wave output
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(1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. Interval Times of 8-Bit Timer/Event Counters 1 and 2
Minimum Interval Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Interval Time MCS = 1 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Resolution MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. Square-Wave Output Ranges of 8-Bit Timer/Event Counters 1 and 2
Minimum Pulse Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 MCS = 0 x 1/fX (800 ns) 29 Maximum Pulse Time MCS = 1 x 1/fX (102.4 s) 210 MCS = 0 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 Resolution MCS = 0 x 1/fX (800 ns)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times When 8-Bit Timer/Event Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter
Minimum Interval Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 MCS = 0 x 1/fX (800 ns) 217 Maximum Interval Time MCS = 1 x 1/fX (26.2 ms) 218 MCS = 0 x 1/fX (52.4 ms) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 Resolution MCS = 0 x 1/fX (800 ns)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s)
219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges When 8-Bit Timer/Event Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter
Minimum Pulse Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 MCS = 0 x 1/fX (800 ns) 217 Maximum Pulse Time MCS = 1 x 1/fX (26.2 ms) 218 MCS = 0 x 1/fX (52.4 ms) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 Resolution MCS = 0 x 1/fX (800 ns)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s)
219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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9.2 8-Bit Timer/Event Counter Configuration
The 8-bit timer/event counter consists of the following hardware. Table 9-5. 8-Bit Timer/Event Counter Configuration
Item Timer register Register Timer outputs Control registers Configuration 8 bits x 2 (TM1, TM2) Compare register: 8 bits x 2 (CR10, CR20) 2 (TO1, TO2) Timer clock select register 1 (TCL1) 8-bit timer mode control register 1 (TMC1) 8-bit timer output control register (TOC1) Port mode register 3 (PM3)Note
Note
See Figure 6-9 Block Diagram of P30 to P37.
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Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter
Internal bus
INTTM1 8-bit compare register 10 (CR10) 8-bit compare register (CR20)
Selector
Note 8-bit timer/event counter output controller 2 4 TO2/P32
Match Match fXX/2 to fXX/2 fXX/2
Selector
9
Selector
11
8-bit timer register 1 (TM1) Clear 4 Selector
TI1/P33
8-bit timer register 2 (TM2) Clear
INTTM2
fXX/2 to fXX/2 fXX/2
11
TI2/P34 Note 4 8-bit timer/ event counter output controller 4 TCL TCL TCL TCL TCL TCL TCL TCL 17 16 15 14 13 12 11 10 Timer clock select register 1 LVS2 LVR2 TOC TOE2 LVS1 LVR1 TOC TOE1 15 11 8-bit timer output control register TO1/P31
Selector
9
TMC12 TCE2 8-bit timer mode control register
TCE1
Internal bus
Note
See Figures 9-2 and 9-3 for details of 8-bit timer/event counter output controllers 1 and 2, respectively.
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Figure 9-2. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
Level F/F (LV1) LVR1 LVS1 TOC11 R Q S INV P31 Output latch PM31Note TO1/P31
INTTM1
TOE1
Note
Bit 1 of port mode register 3 (PM3) The section in the broken lines is the output controller.
Remark
Figure 9-3. Block Diagram of 8-Bit Timer/Event Counter Output Controller 2
Level F/F (LV2) fSCK LVR2 LVS2 TOC15 R Q S INV P32 Output latch PM32Note TO2/P32
INTTM2
TOE2
Note
Bit 2 of port mode register 3 (PM3)
Remarks 1. The section in the broken lines is the output controller. 2. fSCK: Serial clock frequency
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(1) Compare registers 10, 20 (CR10, CR20) CR10 and CR20 are 8-bit registers used to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. When the compare register is used as 8-bit timer/event counter, between values 00H and FFH can be set. When the compare register is used as 16-bit timer/event counter, between values 0000H and FFFFH can be set. RESET input makes CR10 and CR20 undefined. Cautions 1. Before changing the set value of 8-bit compare registers 10 and 20 (CR10 and CR20) while the 16-bit timer/counter is being used, stop the operation of each of the 8-bit timer/event counters. 2. When the new values of CR10 and CR20 are less than the count values of the 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow, and start counting again from 0. If the new values of CR10 and CR20 are less than the old values, therefore, it is necessary to restart the timers after changing the values of CR10 and CR20. (2) 8-bit timer registers 1, 2 (TM1, TM2) TM1 and TM2 are 8-bit registers used to count count pulses. When TM1 and TM2 are used in the 8-bit timer x 2-channel mode, they are read with an 8-bit memory manipulation instruction. When TM1 and TM2 are used as 16-bit timer x 1-channel mode, 16-bit timer register (TMS) is read with a 16-bit memory manipulation instruction. RESET input clears TM1 and TM2 to 00H.
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9.3 8-Bit Timer/Event Counter Control Registers
The following four registers are used to control the 8-bit timer/event counter. * Timer clock select register 1 (TCL1) * 8-bit timer mode control register 1 (TMC1) * 8-bit timer output control register (TOC1) * Port mode register 3 (PM3) (1) Timer clock select register 1 (TCL1) This register sets the count clock of 8-bit timer registers 1 and 2. TCL1 is set with an 8-bit memory manipulation instruction. RESET input clears TCL1 to 00H.
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Figure 9-4. Format of Timer Clock Select Register 1
Symbol 7 6 5 4 3 2 1 0 Address FF41H After reset 00H R/W R/W
TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
TCL13 TCL12 TCL11 TCL10
8-bit timer register 1 count clock selection MCS = 1 MCS = 0
0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
TI1 falling edge TI1 rising edge fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2
2 3 4 5
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2 3 4 5
(2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz)
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2
(1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz)
3 4 5 6
6
6
7
7 8 9 11
7 8 9 11
8 9 10 12
Other than above
Setting prohibited
TCL17 TCL16 TCL15 TCL14
8-bit timer register 2 count clock selection MCS = 1 MCS = 0
0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
TI2 falling edge TI2 rising edge fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2
2 3 4 5
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2 3 4 5
(2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (2.4 kHz)
fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2 fX/2
2
(1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) (1.2 kHz)
3 4 5 6
6
6
7
7 8 9 11
7 8 9 11
8 9 10 12
Other than above
Setting prohibited
Caution When rewriting TCL1 to other data, stop the timer operation beforehand. Remarks 1. 2. 3. 4. 5. 6. fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency TI1: 8-bit timer register 1 input pin TI2: 8-bit timer register 2 input pin MCS: Bit 0 of oscillation mode select register (OSMS) Values in parentheses apply to operation with fX = 5.0 MHz
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(2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer registers 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC1 to 00H. Figure 9-5. Format of 8-Bit Timer Mode Control Register 1
Symbol TMC1 7 0 6 0 5 0 4 0 3 0 2 <1> <0> Address FF49H After reset 00H R/W R/W
TMC12 TCE2 TCE1
TCE1 0 1
8-bit timer register 1 operation control Operation stopped (TM1 is cleared to 0) Operation enabled
TCE2 0 1
8-bit timer register 2 operation control Operation stopped (TM2 is cleared to 0) Operation enabled
TMC12 0 1
Operating mode selection 8-bit timer register x 2-channel mode (TM1, TM2) 16-bit timer register x 1-channel mode (TMS)
Cautions 1. Switch the operating mode after stopping timer operation. 2. When used as a 16-bit timer register (TMS), TCE1 should be used for operation enable/ stop.
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(3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output controllers 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TOC1 to 00H. Figure 9-6. Format of 8-Bit Timer Output Control Register
Symbol <7> <6> 5 <4> <3> <2> 1 <0> Address FF4FH After reset 00H R/W R/W
TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1
TOE1 0 1
8-bit timer/event counter 1 outptut control Output disabled (port mode) Output enabled
TOC11 8-bit timer/event counter 1 timer output F/F control 0 1 Inverted operation disabled Inverted operation enabled
LVS1 LVR1 8-bit timer/event counter 1 timer output F/F status set 0 0 1 1 0 1 0 1 Unchanged Timer output F/F is reset to 0 Timer output F/F is set to 1 Setting prohibited
TOE2 0 1
8-bit timer/event counter 2 output control Output disabled (port mode) Output enabled
TOC15 8-bit timer/event counter 2 timer output F/F control 0 1 Inverted operation disabled Inverted operation enabled
LVS2 LVR2 8-bit timer/event counter 2 timer output F/F status set 0 0 1 1 0 1 0 1 Unchanged Timer output F/F is reset to 0 Timer output F/F is set to 1 Setting prohibited
Cautions 1. Be sure to set TOC1 after stopping timer operation. 2. After data setting, 0 is read from LVS1, LVS2, LVR1, and LVR2 when they are read.
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(4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and the output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 9-7. Format of Port Mode Register 3
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
After reset FFH
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin input/output mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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9.4 Operations of 8-Bit Timer/Event Counters 1 and 2
9.4.1 8-bit timer/event counter mode (1) Interval timer operations 8-bit timer/event counters 1 and 2 operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). When the count values of 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated. The count clock of TM1 can be selected using bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1). The count clock of TM2 can be selected using bits 4 to 7 (TCL14 to TCL17) of timer clock select register 1 (TCL1). For the operation when the value of the compare register is changed during a timer count operation, see 9.5 (3) Operation after compare register change during timer count operation. Figure 9-8. Interval Timer Operation Timing
t
Count clock
TM1 count value
00
01
N
00 Clear
01
N
00 Clear
01
N
Count start
CR10
N
N
N
N
INTTM1 Interrupt request acknowledge Interrupt request acknowledge
TO1
Interval time
Interval time
Interval time
Remark
Interval time = (N + 1) x t : N = 00H to FFH
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Table 9-6. Interval Time of 8-Bit Timer/Event Counter 1
TCL13 TCL12 TCL11 TCL10 Minimum Interval Time MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) MCS = 0 28 28 29 Maximum Interval Time MCS = 1 MCS = 0 Resolution MCS = 1 MCS = 0
x TI1 input cycle x TI1 input cycle x 1/fX (204.8 s) 210 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms)
TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
x 1/fX (102.4 s)
0
1
1
1
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms)
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Other than above
Setting prohibited
Remarks 1. fX: 2. MCS:
Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
3. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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Table 9-7. Interval Time of 8-Bit Timer/Event Counter 2
TCL17 TCL16 TCL15 TCL14 Minimum Interval Time MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 TI2 input cycle TI2 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) MCS = 0 28 Maximum Interval Time MCS = 1 MCS = 0 Resolution MCS = 1 MCS = 0
x TI2 input cycle
TI2 input edge cycle TI2 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
28 x TI2 input cycle 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms)
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Other than above
Setting prohibited
Remarks 1. fX: 2. MCS:
Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
3. TCL14 to TCL17: Bits 4 to 7 of timer clock select register 1 (TCL1) 4. Values in parentheses apply to operation with fX = 5.0 MHz
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(2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins using 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified by the timer clock select register (TCL1) is input. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated. Figure 9-9. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 pin input
TM1 count value
00
01
02
03
04
05
N-1
N
00
01
02
03
CR10
N
INTTM1
Remark
N = 00H to FFH
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(3) Square-wave output operation 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 9-8. Square-Wave Output Ranges of 8-Bit Timer/Event Counters 1 and 2
Minimum Pulse Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 MCS = 0 x 1/fX (800 ns) 29 Maximum Pulse Time MCS = 1 x 1/fX (102.4 s) 210 MCS = 0 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 Resolution MCS = 0 x 1/fX (800 ns)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms)
23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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Figure 9-10. Square-Wave Output Operation Timing
Count clock
TM1 count value
00
01
02
N-1
N
00
01
02
N-1
N
00
Count start CR10 N N
TO1Note
Note
The initial value of the TO1 output can be set by bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1).
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9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected by using bits 0 to 3 (TCL10 to TCL13) of the timer clock select register (TCL1), and the overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock for 8-bit timer/event counter 2 (TM2). The counting operation is enabled or disabled in this mode by using bit 0 (TCE1) of TMC1. (1) Operation as interval timer The 16-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at intervals of the count values set in advance to the 2 channels of the 8-bit compare registers (CR10 and CR20). When setting a count value, assign the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10. For the count values that can be set (interval time), see Table 9-9. When the value of 8-bit timer register 1 (TM1) matches the value of CR10 and the value of 8-bit timer register 2 (TM1) matches the value of CR20, the values of TM1 and TM2 are cleared to 0, and at the same time, an interrupt request signal (INTTM2) is generated. For the operation timing of the interval timer, see Figure 911. Select the count clock by using bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1). The overflow signal of TM1 is used as the count clock for TM2. Figure 9-11. Interval Timer Operation Timing
t
Count clock
TMS (TM1, TM2) count value
0000
0001
N
0000 0001 Clear
N
0000 0001 Clear
N
Count start
CR10, CR20
N
N
N
N
INTTM2 Interrupt request acknowledge Interrupt request acknowledge
TO2
Interval time
Interval time
Interval time
Remark
Interval time = (N + 1) x t : N = 0000H to FFFFH
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output controller 1 is inverted. Thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation instruction.
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Table 9-9. Interval Times When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
TCL13 TCL12 TCL11 TCL10 Minimum Interval Time MCS = 1 0 0 0 0 0 1 0 0 1 0 1 0 TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) MCS = 0 28 Maximum Interval Time MCS = 1 MCS = 0 Resolution MCS = 1 MCS = 0
x TI1 input cycle
TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
28 x TI1 input cycle 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s)
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Other than above
Setting prohibited
Remarks 1. fX: 2. MCS:
Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
3. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin using 2-channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input. When TM1 overflows as a result, TM2 is incremented with the overflow signal used as its count clock. Either the rising or falling edge can be selected. When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and CR20), TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated. Figure 9-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 pin input
TM1, TM2 count value
0000 0001 0002 0003 0004 0005
N-1
N
0000 0001 0002 0003
CR10, CR20
N
INTTM2
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output controller 1 is inverted. Thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation instruction.
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(3) Square-wave output operation 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (CR10 and CR20). To set a count value, set the value of the higher 8 bits to CR20, and the value of the lower 8 bits to CR10. The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 9-10. Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
Minimum Pulse Time MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Time MCS = 1 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 227 x 1/fX (26.8 s) MCS = 0 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) MCS = 1 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 211 x 1/fX (409.6 s) Resolution MCS = 0 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX:
Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS) 3. Values in parentheses apply to operation with fX = 5.0 MHz.
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Figure 9-13. Square-Wave Output Operation Timing
Count clock TM1 TM2 CR10 CR20 TO2 Count start
00H 00H
01H
N N+1
FFH 00H 01H
FFH 00H 02H
FFH 00H 01H M-1 M
N 00H 01H 00H
N M
Interval time Level inversion counter clear
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9.5 Cautions on 8-Bit Timer/Event Counters 1 and 2
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously to the count pulse. Figure 9-14. Start Timing of 8-Bit Timer Registers 1 and 2
Count pulse
TM1, TM2 count value
00H
01H
02H
03H
04H
Timer start
(2) 8-bit compare register 10 and 20 setting 8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H. Thus, when these 8-bit compare registers are used as event counters, a one-pulse count operation can be carried out. When the 8-bit compare register is used as 16-bit timer/event counter, write data to CR10 and CR20 after setting bit 0 (TCE1) of the 8-bit timer mode control register (TMC1) and stopping timer operation. Figure 9-15. External Event Counter Operation Timing
TI1, TI2, input
CR10, CR20
00H
TM1, TM2 count value
00H
00H
00H
00H
TO1, TO2
Interrupt request flag
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(3) Operation after compare register change during timer count operation If the values after 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of the 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value after CR10 and CR20 change (M) is smaller than value before the change (N), it is necessary to restart the timer after changing CR10 and CR20. Figure 9-16. Timing After Compare Register Change During Timer Count Operation
Count pulse
CR10, CR20
N
M
TM1, TM2 count value
X-1
X
FFH
00H
01H
02H
Remark
N>X>M
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10.1 Watch Timer Functions
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. Caution 0.5-second intervals cannot be generated with the 5.0 MHz main system clock. Switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals. Remark fXX: Watch timer clock frequency (fX/27 or fXT) fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency (2) Interval timer Interrupt requests (INTTM3) are generated at the preset time interval. Table 10-1. Interval Timer Interval Time
Interval Time 24 x 1/fW 25 26 27 28 29 x 1/fW x 1/fW x 1/fW x 1/fW x 1/fW When Operated at fXX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms When Operated at fXX = 4.19 MHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
Remark
fXX: Main system clock frequency (fX or fX/2) fX: fW: Main system clock oscillation frequency Watch timer clock frequency (fXX/27 or fXT) fXT: Subsystem clock oscillation frequency
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10.2 Watch Timer Configuration
The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration
Item Counter Control registers 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Configuration
10.3 Watch Timer Control Registers
The following two registers are used to control the watch timer. * Timer clock select register 2 (TCL2) * Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) (see Figure 10-2.) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer output frequency.
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Figure 10-1. Watch Timer Block Diagram
TMC21 fW 214
Selector
fW
Prescaler fW fW fW 24 25 26 fW fW 27 28 fW 29
Selector
f XX /2
7
Clear
Selector
5-bit counter Clear
INTWT
f XT
fW 213
Selector
INTTM3 To 16-bit timer/ event counter
3
TCL24 Timer clock select register 2
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch timer mode control register Internal bus
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Figure 10-2. Format of Timer Clock Select Register 2
Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After reset 00H R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog timer count clock selection (see CHAPTER 11 WATCHDOG TIMER) MCS = 1 MCS = 0 fX /2 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz)
4
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fXX/2
3
fX /2 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz)
3
fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211
TCL24
Watch timer count clock selection MCS = 1 MCS = 0 fX /28 (19.5 kHz)
0 1
fXX/27 fXT (32.768 kHz)
fX /27 (39.1 kHz)
TCL27 TCL26 TCL25
Buzzer output frequency selection (see CHAPTER 13 BUZZER OUTPUT CONTROLLER) MCS = 1 MCS = 0
0 1 1 1 1
x 0 0 1 1
x 0 1 0 1
Buzzer output disabled fXX/29 fXX/210 fXX/211 Setting prohibited fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz)
Caution When changing the count clock, be sure to stop operation of the watch timer before rewriting TCL2 (stopping operation is not necessary when rewriting the same data). Remarks 1. fXX: 2. fX: 3. fXT: 4. x: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency don't care
5. MCS: Bit 0 of oscillation mode select register (OSMS) 6. Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
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(2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC2 to 00H. Figure 10-3. Format of Watch Timer Mode Control Register
Symbol TMC2 7 0 6 5 4 3 2 1 0 Address FF4AH After reset 00H R/W R/W
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
TMC20 0 1
Watch operating mode selection Normal operating mode (flag set at fW/214 ) Fast feed operating mode (flag set at fW/25)
TMC21 0 1 Clear after operation stop Operation enable
Prescaler operation control
TMC22 0 1 Clear after operation stop Operation enable
5-bit counter operation control
TMC23 fXX = 5.0 MHz operation 0 1 2 /fW (0.4 sec) 213/fW (0.2 sec)
14
Watch flag set time selection fXX = 4.19 MHz operation 2 /fW (0.5 sec) 213/fW (0.25 sec)
14
fXT = 32.768 kHz operation 214/fW (0.5 sec) 213/fW (0.25 sec)
TMC26 TMC25 TMC24 fXX = 5.0 MHz operation 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 2 /fW (410 s)
4
Prescaler interval time selection fXX = 4.19 MHz operation 2 /fW (488 s)
4
fXT = 32.768 kHz operation 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms)
25/fW (819 s) 26/fW (1.64 ms) 27/fW (3.28 ms) 28/fW (6.55 ms) 29/fW (13.1 ms) Setting prohibited
25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms)
Other than above
Caution When the watch timer is used, the prescaler should not be cleared frequently. Remarks 1. fW: 2. fXX: 3. fX: 4. fXT: Watch timer clock frequency (fXX/27 or fXT) Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency
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10.4 Watch Timer Operations
10.4.1 Watch timer operation When the 32.768 kHz subsystem clock or 4.19 MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at a constant time interval. When WTMK = 0, the standby state (STOP mode/HALT mode) can be cleared by setting WTIF to 1. When bit 2 (TMC22) of the watch timer mode control register (TMC2) is cleared to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be achieved by clearing TMC22 to 0 (maximum error: 26.2 ms when operated at fXX = 5.0 MHz). 10.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value. The interval time can be selected using bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register (TMC2). Table 10-3. Interval Timer Interval Time
TMC26 TMC25 TMC24 Interval Time 24 x 1/fW 25 26 27 28 29 x 1/fW x 1/fW x 1/fW x 1/fW x 1/fW When Operated at fXX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms When Operated at fXX = 4.19 MHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
0 0 0 0 1 1
0 0 1 1 0 0 Other than above
0 1 0 1 0 1
Setting prohibited
Remark
fXX: fX: fXT: fW:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency Watch timer clock frequency (fXX/27 or fXT)
TMC24 to TMC26: Bits 4 to 6 of watch timer mode control register (TMC2)
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11.1 Watchdog Timer Functions
The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM) (the watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop is detected. Upon detection of the program loop, a non-maskable interrupt request or RESET can be generated. Table 11-1. Watchdog Timer Program Loop Detection Times
Runaway Detection Time 211 212 213 214 215 216 217 219 x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX 211 212 213 214 215 216 217 219 MCS = 1 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (104.9 ms) 212 213 214 215 216 217 218 220 MCS = 0 x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (52.4 ms) x 1/fX (209.7 ms)
Remarks 1. fXX: 2. fX:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS: Bit 0 of oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times
Interval Time 211 x 1/fXX 212 x 1/fXX 213 x 1/fXX 214 x 1/fXX 215 x 1/fXX 216 x 1/fXX 217 x 1/fXX 219 x 1/fXX MCS = 1 211 x 1/fX (410 s) 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 219 x 1/fX (104.9 ms) MCS = 0 212 x 1/fX (819 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms)
Remarks 1. fXX: 2. fX:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS: Bit 0 of oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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11.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration
Item Control registers Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM)
Figure 11-1. Watchdog Timer Block Diagram
Internal bus f XX /23 Prescaler fXX fXX fXX fXX fXX fXX f XX 24 25 26 27 28 29 211 TMMK4 RUN TMIF4 8-bit counter Controller INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request RUN WDTM4 WDTM3 Watchdog timer mode register Internal bus
TCL22 TCL21 TCL20 Timer clock select register 2
240
Selector
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11.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer output frequency.
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Figure 11-2. Format of Timer Clock Select Register 2
After reset 00H
Symbol
7
6
5
4
3 0
2
1
0
Address FF42H
R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog timer count clock selection MCS = 1 MCS = 0 fX /2
4
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fXX/2
3
fX /2 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz)
3
(313 kHz)
fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211
fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz)
TCL24
Watch timer count clock selection (see CHAPTER 10 WATCH TIMER) MCS = 1 MCS = 0 fX /2 (19.5 kHz)
8
0 1
fXX/2
7
fX /2 (39.1 kHz)
7
fXT (32.768 kHz)
TCL27 TCL26 TCL25
Buzzer output frequency selection (see CHAPTER 13 BUZZER OUTPUT CONTROLLER) MCS = 1 MCS = 0
0 1 1 1 1
x 0 0 1 1
x 0 1 0 1
Buzzer output disable fXX/29 fXX/210 fXX/211 Setting prohibited fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz)
Caution Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation has started is prohibited. Remarks 1. fXX: 2. fX: 3. fXT: 4. x: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency don't care
5. MCS: Bit 0 of oscillation mode select register (OSMS) 6. Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
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(2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 11-3. Format of Watchdog Timer Mode Register
Symbol <7> 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H WDTM4 WDTM3 0 x After reset 00H R/W R/W
WDTM RUM
WDTM4 WDTM3
Watchdog timer operation mode selection selectionNote 1 Interval timer modeNote 2 (Maskable interrupt request occurs upon generation of an overflow.) Watchdog timer mode 1 (Non-maskable interrupt request occurs upon generation of an overflow.) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.)
1
0
1
1
RUN 0 1
Watchdog timer operation mode selectionNote 3 Count stop Counter is cleared and counting starts.
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 2. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1. 3. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. Cautions 1. When RUN is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by timer clock select register 2 (TCL2). 2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (TMIF4) is 0, and then set WDTM4 to 1. If WDTM4 is set to 1 when TMIF4 is 1, the non-maskable interrupt request occurs, regardless of the contents of WDTM3. Remark x: don't care
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11.4 Watchdog Timer Operations
11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect an inadvertent program loop. The watchdog timer count clock (program loop detection time interval) can be selected using bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set loop detection time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the program loop detection time has elapsed, system reset or a non-maskable interrupt request is generated according to the value of WDTM bit 3 (WDTM3). By setting RUN to 1, the watchdog timer can be cleared. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions 1. The actual loop detection time may be shorter than the set time by a maximum of 0.5%. 2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation is stopped. Table 11-4. Watchdog Timer Program Loop Detection Time
TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 Runaway Detection Time 211 212 213 214 215 216 217 219 x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX 211 212 213 214 215 216 217 219 MCS = 1 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (104.9 ms) 212 213 214 215 216 217 218 220 MCS = 0 x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (52.4 ms) x 1/fX (209.7 ms)
Remarks 1. fXX: 2. fX: 3. MCS:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
4. TCL20 to TCL22: Bits 0 to 2 of timer clock select register 2 (TCL2) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0. The count clock (interval time) can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer. When the watchdog timer operates as interval timer, the interrupt mask flag (TMMK4) and priority specification flag (TMPR4) are validated and a maskable interrupt request (INTWDT) can be generated. Among the maskable interrupt requests, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) of WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. 2. The interval time just after setting by WDTM may be shorter than the set time by a maximum of 0.5%. 3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation is stopped. Table 11-5. Interval Timer Interval Time
TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 211 212 213 214 215 216 217 219 Interval Time x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX x 1/fXX 211 212 213 214 215 216 217 219 MCS = 1 x 1/fX (410 s) x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (104.9 ms) 212 213 214 215 216 217 218 220 MCS = 0 x 1/fX (819 s) x 1/fX (1.64 ms) x 1/fX (3.28 ms) x 1/fX (6.55 ms) x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (52.4 ms) x 1/fX (209.7 ms)
Remarks 1. fXX: 2. fX: 3. MCS:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Bit 0 of oscillation mode select register (OSMS)
4. TCL20 to TCL22: Bits 0 to 2 of timer clock select register 2 (TCL2) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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CHAPTER 12 CLOCK OUTPUT CONTROLLER
12.1 Clock Output Controller Functions
The clock output controller is used for carrier output during remote controlled transmission and clock output for supply to peripheral LSI devices. The clock selected by timer clock select register 0 (TCL0) is output from the PCL/ P35 pin. Follow the procedure below to output clock pulses. (1) Select the clock pulse output frequency (with clock pulse output disabled) using bits 0 to 3 (TCL00 to TCL03) of TCL0. (2) Set the P35 output latch to 0. (3) Set bit 5 (PM35) of port mode register 3 (PM3) to 0 (set to output mode). (4) Set bit 7 (CLOE) of timer clock select register 0 (TCL0) to 1. Caution Clock output cannot be used when the P35 output latch is set to 1. Remark When clock output enable/disable is switched, the clock output controller does not output pulses with small widths (see the portions marked with * in Figure 12-1). Figure 12-1. Remote Controlled Output Application Example
CLOE
* PCL/P35 pin output
*
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12.2 Clock Output Controller Configuration
The clock output controller consists of the following hardware. Table 12-1. Clock Output Controller Configuration
Item Control registers Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3)
Figure 12-2. Clock Output Controller Block Diagram
fXX fXX /2 fXX /22 fXX /24 fXX /25 fXX /26 fXX /27 fXT 4 fXX /23
Selector
Synchronizing circuit
PCL /P35
CLOE TCL03 TCL02 TCL01 TCL00 Timer clock select register 0
P35 Output latch
PM35 Port mode register 3
Internal Bus
12.3 Clock Output Function Control Registers
The following two registers are used to control the clock output function. * Timer clock select register 0 (TCL0) * Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets the PCL output clock. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TCL0 to 00H. Remark Besides setting the PCL output clock, TCL0 sets the 16-bit timer register count clock.
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Figure 12-3. Format of Timer Clock Select Register 0
Symbol <7> 6 5 4 3 2 1 0 Address FF40H After reset 00H R/W R/W
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00
PCL output clock selection MCS = 1 MCS = 0
0 0 0 0 1 1 1 1 1
0 1 1 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
fXT (32.768 kHz) fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fX (5.0 MHz) fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz)
fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz)
Other than above
Setting prohibited
TCL06 TCL05 TCL04
16-bit timer register count clock selection MCS = 1 MCS = 0
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 0 1
TI00 (valid edge specifiable) 2fXX fXX fXX/2 fXX/22 Setting prohibited fX (5.0 MHz) fX (5.0 MHz)
fX /2 (2.5 MHz) fX /22 (1.25 MHz) fX /23 (625 kHz)
fX /2 (2.5 MHz) fX /22 (1.25 MHz)
Watch timer output (INTTM3) Setting prohibited
Other than above
CLOE 0 1 Output disabled Output enabled
PCL output control
Cautions 1. The TI00/P00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and the sampling clock frequency is selected by the sampling clock select register (SCS). 2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory manipulation instruction. 3. When reading the count value when TI00 has been specified as the TM0 count clock, the value should be read from TM0, not from the 16-bit capture/compare register (CR01). 4. When rewriting TCL0 to other data, stop the clock operation beforehand.
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Remarks 1. fXX: 2. fX: 3. fXT:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency
4. TI00: 16-bit timer/event counter input pin 5. TM0: 16-bit timer register 6. MCS: Bit 0 of oscillation mode select register (OSMS) 7. Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output, set PM35 and the output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 12-4. Format of Port Mode Register 3
After reset FFH
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin input/output mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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CHAPTER 13 BUZZER OUTPUT CONTROLLER
13.1 Buzzer Output Controller Functions
The buzzer output controller outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected by timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. (1) Select the buzzer output frequency using bits 5 to 7 (TCL25 to TCL27) of TCL2. (2) Set the P36 output latch to 0. (3) Set bit 6 (PM36) of port mode register 3 (PM3) to 0 (set to output mode). Caution Buzzer output cannot be used when the P36 output latch is set to 1.
13.2 Buzzer Output Controller Configuration
The buzzer output controller consists of the following hardware. Table 13-1. Buzzer Output Controller Configuration
Item Control registers Configuration Timer clock select register 2 (TCL2) Port mode register 3 (PM3)
Figure 13-1. Buzzer Output Controller Block Diagram
fXX /210 fXX /211
Selector
fXX /29
BUZ/P36
3
TCL27 TCL26 TCL25 Timer clock select register 2
P36 Output latch
PM36 Port mode register 3
Internal bus
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13.3 Buzzer Output Function Control Registers
The following two registers are used to control the buzzer output function. * Timer clock select register 2 (TCL2) * Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the watchdog timer count clock.
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Figure 13-2. Format of Timer Clock Select Register 2
After reset 00H
Symbol
7
6
5
4
3 0
2
1
0
Address FF42H
R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
TCL22 TCL21 TCL20
Watchdog timer count clock selection (see CHAPTER 11 WATCHDOG TIMER) MCS = 1 MCS = 0 fX /2
4
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
fXX/2
3
fX /2 (625 kHz) fX /24 (313 kHz) fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /211 (2.4 kHz)
3
(313 kHz)
fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/211
fX /25 (156 kHz) fX /26 (78.1 kHz) fX /27 (39.1 kHz) fX /28 (19.5 kHz) fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /212 (1.2 kHz)
TCL24
Watch timer count clock selection (see CHAPTER 10 WATCH TIMER) MCS = 1 MCS = 0 fX /2 (19.5 kHz)
8
0 1
fXX/2
7
fX /2 (39.1 kHz)
7
fXT (32.768 kHz)
TCL27 TCL26 TCL25
Buzzer output frequency selection MCS = 1 MCS = 0
0 1 1 1 1
x 0 0 1 1
x 0 1 0 1
Buzzer output disabled fXX/29 fXX/210 fXX/211 Setting prohibited fX /29 (9.8 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /210 (4.9 kHz) fX /211 (2.4 kHz) fX /212 (1.2 kHz)
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting TCL2 (stop operation is not necessary when rewriting the same data). The operation is stopped by the following methods. * Buzzer output: Input 0 to bit 7 of TCL2 (TCL27) * Watch timer: Input 0 to bit 2 (TMC22) of watch timer mode control register 2 (TMC2) 2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation has started is prohibited. Remarks 1. fXX: 2. fX: 3. fXT: 4. x: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Subsystem clock oscillation frequency don't care
5. MCS: Bit 0 of oscillation mode select register (OSMS) 6. Values in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
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(2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output, clear PM36 and the output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 13-3. Format of Port Mode Register 3
After reset FFH
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin input/output mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
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14.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). A/D conversion can be started in the following two ways. (1) Hardware start Conversion is started by trigger input (INTP3). (2) Software start Conversion is started by setting the A/D converter mode register (ADM). One analog input channel is selected from ANI0 to ANI7 and A/D conversion is carried out. In the case of hardware start, A/D conversion stops when an A/D conversion operation ends, and an interrupt request (INTAD) is generated. In the case of software start, A/D conversion is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
14.2 A/D Converter Configuration
The A/D converter consists of the following hardware. Table 14-1. A/D Converter Configuration
Item Analog inputs Control registers Configuration 8 channels (ANI0 to ANI7) A/D converter mode register (ADM) A/D converter input select register (ADIS) External interrupt mode register 1 (INTM1) Successive approximation register (SAR) A/D conversion result register (ADCR)
Registers
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Figure 14-1. A/D Converter Block Diagram
Internal bus
A/ D converter input select register ADIS3 ADIS2 ADIS1 ADIS0 4 ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17
Series resistor string
Tap selector
Note 1
Note 2
Sample & hold circuit
Selector
Selector
Voltage comparator
AVSS
AVREF0 (also functions as analog power supply) AVSS
Successive approximation register (SAR)
3 ADM1 to ADM3 INTP3/P03 ES40, ES41Note 3 3 Trigger enable CS TRG FR1 FR0 ADM3 ADM2 ADM1 HSC A/D converter mode register A/D conversion result register (ADCR) Edge detector
Controller
INTAD INTP3
Internal bus
Notes 1. Selector to select the number of channels to be used for analog input. 2. Selector to select the channel for A/D conversion. 3. ES40, ES41: Bits 0 and 1 of external interrupt mode register 1 (INTM1)
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(1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR). (2) A/D conversion result register (ADCR) This register holds the A/D conversion result. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). ADCR is read with an 8-bit memory manipulation instruction. RESET input makes ADCR undefined. (3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AVREF0 and AVSS, and generates a voltage to be compared with the analog input. (6) ANI0 to ANI7 pins These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter. Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used as I/O ports. Cautions 1. Use the ANI0 to ANI7 input voltages within the specified range. If a voltage higher than or equal to AVREF0 or lower than or equal to AVSS is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. The analog input pins (ANI0 to ANI7) also function as I/O port pins (port 1). When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtained due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
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(7) AVREF0 pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF0 and AVSS. The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF0 pin to AVSS level in standby mode. This pin also serves as an analog power supply pin. Supply power to this pin when the A/D converter is used. Caution A series resistor string of approximately 10 k is connected between the AVREF0 pin and AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between AVREF0 pin and the AVSS pin, resulting in a large reference voltage error. (8) AVSS pin This is a GND potential pin of the A/D converter. Keep it at the same potential as the VSS0 pin when not using the A/D converter.
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14.3 A/D Converter Control Registers
The following three registers are used to control the A/D converter. * A/D converter mode register (ADM) * A/D converter input select register (ADIS) * External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger. ADM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM to 01H.
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Figure 14-2. Format of A/D Converter Mode Register
Symbol ADM <7> CS <6> TRG 5 FR1 4 3 2 1 0 Address FF80H After reset 01H R/W R/W
FR0 ADM3 ADM2 ADM1 HSC
ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Analog input channel selection
FR1
FR0
HSC
A/D conversion time selectionNote 1 fX = 5.0 MHz operation MCS = 1 MCS = 0 160/fX (32.0 s)
Note 2
fX = 4.19 MHz operation MCS = 1 80/fX (19.1 s) 40/fX (Setting prohibited 50/fX (Setting prohibited 100/fX (23.8 s)
Note 2
MCS = 0 160/fX (38.1 s) ) 80/fX (19.1 s) ) 100/fX (23.8 s) 200/fX (47.7 s)
0 0 1 1
0 1 0 0
1 1 0 1
80/fX (16.0 s) 40/fX (Setting prohibited 50/fX (Setting prohibited 100/fX (20.0 s) Setting prohibited
) 80/fX (16.0 s) ) 100/fX (20.0 s) 200/fX (40.0 s)
Note 2
Note 2
Other than above
TRG 0 1 No external trigger (software starts)
External trigger selection
Conversion started by external trigger (hardware starts)
CS 0 1 Operation stop Operation start
A/D conversion operation control
Notes 1. Set so that the A/D conversion time is 16 s or more. 2. Setting is prohibited because the A/D conversion time is less than 16 s with fX set to this condition. Cautions 1. The following sequence is recommended for reducing the power consumption of the A/D converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 2. When restarting a stopped A/D conversion operation, start the A/D conversion operation after clearing the interrupt request flag (ADIF) to 0. Remarks 1. fX: Main system clock oscillation frequency
2. MCS: Bit 0 of oscillation mode select register (OSMS)
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(2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as I/O ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input clears ADIS to 00H. Cautions 1. Set the analog input channel using the following procedure. (1) Set the number of analog input channels using ADIS. (2) Using the A/D converter mode register (ADM), select one channel to undergo A/D conversion from among the channels set to analog input by ADIS. 2. No internal pull-up resistor can be used for the channels set to analog input by ADIS, irrespective of the value of bit 1 (PUO1) of pull-up resistor option register L (PUOL). Figure 14-3. Format of A/D Converter Input Select Register
Symbol ADIS 7 0 6 0 5 0 4 0 3 2 1 0 Address FF84H After reset 00H R/W R/W
ADIS3 ADIS2 ADIS1 ADIS0
ADIS3 ADIS2 ADIS1 ADIS0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
Number of analog input channel selection No analog input channel (P10 to P17) 1 channels (ANI0, P11 to P17) 2 channels (ANI0, ANI1, P12 to P17) 3 channels (ANI0 to ANI2, P13 to P17) 4 channels (ANI0 to ANI3, P14 to P17) 5 channels (ANI0 to ANI4, P15 to P17) 6 channels (ANI0 to ANI5, P16, P17) 7 channels (ANI0 to ANI6, P17) 8 channels (ANI0 to ANI7) Setting prohibited
Other than above
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(3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP5. INTM1 is set with an 8-bit memory manipulation instruction. RESET input clears INTM1 to 00H. Figure 14-4. Format of External Interrupt Mode Register 1
After reset 00H
Symbol INTM1
7 0
6 0
5
4
3
2
1
0
Address FFEDH
R/W R/W
ES61 ES60 ES51 ES50 ES41 ES40
ES41 ES40 0 0 1 1 0 1 0 1
INTP3 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES51 ES50 0 0 1 1 0 1 0 1
INTP4 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES61 ES60 0 0 1 1 0 1 0 1
INTP5 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
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14.4 A/D Converter Operations
14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels using the A/D converter input select register (ADIS). (2) From among the analog input channels set by ADIS, select one channel for A/D conversion using the A/D converter mode register (ADM). (3) Sample the voltage input to the selected analog input channel using the sample & hold circuit. (4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until the end of A/D conversion. (5) Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF0 by the tap selector. (6) The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF0, the MSB of SAR remains set. If the input is smaller than (1/2) AVREF0, the MSB is reset. (7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. * Bit 7 = 1: (3/4) AVREF0 * Bit 7 = 0: (1/4) AVREF0 The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows. * Analog input voltage Voltage tap: Bit 6 = 1 * Analog input voltage < Voltage tap: Bit 6 = 0 (8) Comparison of this sort continues up to bit 0 of SAR. (9) Upon completion of the comparison of 8 bits, a valid digital result remains in SAR and that value is transferred to and latched in the A/D conversion result register (ADCR). At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
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Figure 14-5. A/D Converter Basic Operation
CS = 0 1, or external trigger, or ADM rewrite A/D conversion start delay time
Conversion time
Sampling time A/D converter operation
Sampling
A/D conversion
SAR
Undefined
80H
C0H or 40H
Conversion result
ADCR
Conversion result
INTAD
CS
A/D conversion operations are performed continuously until bit 7 (CS) of the AD converter mode register (ADM) is reset to 0 by software. RESET input makes ADCR undefined. Check the completion of A/D conversion by using the A/D conversion end interrupt request flag (ADIF). Table 14-2. A/D Converter Sampling Time and A/D Conversion Start Delay Time
FR01 FR00 HS0C Conversion TimeNote 1 Sampling Time A/D Conversion Start Delay Time
MCS = 1 0 0 1 1 0 1 0 0 1 1 0 1 80/fX (16.0 s) 40/fX (setting prohibitedNote 2) 50/fX (setting prohibitedNote 2) 100/fX (20.0 s) Setting prohibited
MCS = 0 160/fX (32.0 s) 80/fX (16.0 s) 100/fX (20.0 s) 200/fX (40.0 s)
MCS = 1 MCS = 0 MCS = 1 MCS = 0 9/fX 4.5/fX 5.25/fX 10.5/fX - 18/fX 9/fX 10.5/fX 21/fX 6/fX 3/fX 4.5/fX 9/fX - 12/fX 6/fX 9/fX 18/fX
Other than above
Notes 1. Set so that the A/D conversion time is 16 s or more. 2. Setting is prohibited because the A/D conversion time is less than 16 s with fX set to this condition. Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 5.0 MHz.
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14.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in the A/D conversion result register (ADCR)) is shown by the following expression. VIN ADCR = INT ( x 256 + 0.5) AVREF0 or (ADCR - 0.5) x Where, AVREF0 VIN < (ADCR + 0.5) x AVREF0 256 256
INT( ): Function which returns integer part of value in parentheses. VIN: ADCR Analog input voltage Value of A/D conversion result register (ADCR) AVREF0: AVREF0 pin voltage
Figure 14-6 shows the relationship between the analog input voltage and the A/D conversion result. Figure 14-6. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
A/D conversion results (ADCR)
253
3
2
1
0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1
Input voltage/AVREF0
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14.4.3 A/D converter operating mode One analog input channel is selected from among ANI0 to ANI7 by the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is started. A/D conversion can be stared in the following two ways. * Hardware start: Conversion is started by trigger input (INTP3). * Software start: Conversion is started by setting ADM. The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is simultaneously generated. (1) A/D conversion by hardware start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 1, the A/D conversion standby state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends the A/D conversion operation and waits for a new external trigger signal to be input. When the external trigger input signal is input again, A/D conversion is carried out from the beginning. If data with CS cleared to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 14-7. A/D Conversion by Hardware Start
INTP3 ADM rewrite CS = 1, TRG = 1 ADM rewrite CS = 1, TRG = 1
A /D conversion
Standby state
ANIn
ANIn
Standby state
ANIn
Standby state
ANIm
ANIm
ANIm
ADCR
ANIn
ANIn
ANIn
ANIm
ANIm
INTAD
Remark
n = 0, 1, ..., 7 m = 0, 1, ..., 7
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(2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively, A/D conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (ADM1 to ADM3) of ADM. Upon termination of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. continues repeatedly until new data is written to ADM. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends the A/D conversion operation and starts A/D conversion on the newly written data. If data with CS cleared to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 14-8. A/D Conversion by Software Start
Conversion start CS = 1, TRG = 0 ADM rewrite CS = 1, TRG = 0 ADM rewrite CS = 0, TRG = 0
The A/D conversion operation
A /D conversion
ANIn
ANIn
ANIn
ANIm
ANIm
Conversion suspended Conversion results are not stored.
Stop
ADCR
ANIn
ANIn
ANIm
INTAD
Remark
n = 0, 1, ..., 7 m = 0, 1, ..., 7
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14.5 How to Read the A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per 1 bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). When the resolution is 8 bits, 1LSB = 1/28 = 1/256 = 0.4%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale offset, full-scale offset, integral linearity error, differential linearity error and errors which are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale offset, full-scale offset, integral linearity error, and differential linearity error in the characteristics table. Figure 14-9. Overall Error Figure 14-10. Quantization Error
1......1
1......1
Ideal line
Digital output
Overall error
Digital output
1/2LSB
Quantization error 1/2LSB
0......0 0 Analog input AVREF0
0......0 0 Analog input AVREF0
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(4) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (5) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling time
Conversion time
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14.6 A/D Converter Cautions
(1) Power consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by stopping the conversion operation (by setting bit 7 (CS) of the A/D converter mode register (ADM) to 0). Figure 14-11 shows how to reduce the current consumption in the standby mode. Figure 14-11. Example of Method of Reducing Current Consumption in Standby Mode
AVREF0
P-ch
CS
Series resistor string AVSS
(2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage of AVREF0 or above or AVSS or below is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined. The conversion values of the other channels may also be affected. (3) Conflicting operations <1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon end of conversion ADCR read is given priority. After the read operation, the new conversion result is written to ADCR. <2> Conflict between ADCR write and external trigger signal input upon end of conversion The external trigger signal is not acknowledged during A/D conversion. Therefore, the external trigger signal is not acknowledged during ADCR write. <3> Conflict between ADCR write and A/D converter mode register (ADM) write or A/D converter input select register (ADIS) write ADM or ADIS write is given priority. ADCR write is not performed, nor is the conversion end interrupt request signal (INTAD) generated.
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(4) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on the AVREF0 and ANI0 to ANI7 pins. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-12 in order to reduce noise. Figure 14-12. Analog Input Pin Handling
If there is possibility that noise whose level is AVREF0 or higher or AVSS or lower may enter, clamp with a diode with a small VF (0.3 V or less). Reference voltage input AVREF0
ANI0 to ANI7 C = 100 to 1,000 pF VDD0
AVSS VSS0
(5) ANI0/P10 to ANI7/P17 pins The analog input pins ANI0 to ANI7 also function as I/O port pins (port 1). When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI7 pins In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth of the conversion time. Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input source 10 k or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 14-12). (7) AVREF0 pin input impedance A series resistor string of approximately 10 k is connected between the AVREF0 pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the AVREF0 pin and the AVSS pin, and there will be a large reference voltage error.
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(8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite. At this time, when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. When the A/D conversion is stopped and then resumed, clear ADIF before it is resumed. Figure 14-13. A/D Conversion End Interrupt Request Generation Timing
ADM rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended.
ADM rewrite (start of ANIn conversion)
A /D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remark
n = 0, 1, ..., 7 m = 0, 1, ..., 7
(9) Conversion result immediately after A/D converter start The first A/D conversion value immediately after A/D conversion is started may not satisfy ratings. Therefore, implement a countermeasure such as polling A/D conversion end interrupt requests (INTAD) to delete the first conversion result.
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(10) Timing at which A/D conversion result is undefined The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of stopping the A/D conversion conflict with each other. Therefore, read the A/D conversion result during the A/D conversion operation. To read the conversion result after stopping the A/D conversion operation, be sure to stop the A/D conversion before the next conversion ends. Figures 14-14 and 14-15 show the timing of reading the conversion result. Figure 14-14. Timing of Reading Conversion Result (When Conversion Result is Undefined)
A/D conversion ends
A/D conversion ends
ADCR INTAD CS
Normal conversion result
Undefined value
Normal conversion result is read.
A/D conversion is stopped.
Undefined value is read.
Figure 14-15. Timing of Reading Conversion Result (When Conversion Result is Normal)
A/D conversion ends
ADCR INTAD CS
Normal conversion result
A/D conversion is stopped.
Normal conversion result is read.
(11) Notes on board design Locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. In particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. Otherwise, the A/D conversion characteristics may be affected by the noise of the digital line. Connect AVSS and VSS0 at one location on the board where the voltages are stable.
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(12) AVREF0 pin Connect a capacitor to the AVREF0 pin to minimize conversion errors due to noise. If an A/D conversion operation has been stopped and then is started, the voltage applied to the AVREF0 pin becomes unstable, causing the accuracy of the A/D conversion to drop. To prevent this, also connect a capacitor to the AVREF0 pin. Figure 14-16 shows an example of connecting a capacitor. Capacitor C1 is effective for noise of low frequency and capacitor C2 is effective for noise of high frequency. Figure 14-16. Example of Connecting Capacitor to AVREF0 Pin
AVREF0 C1 C2 AVSS
Remark
C1: 4.7 F to 10 F (reference value) C2: 0.01 F to 0.1 F (reference value) Connect C2 as close to the pin as possible.
(13) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance To complete sampling within the sampling time with sufficient A/D conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. Figure 14-17 shows the internal equivalent circuit of the ANI0 to ANI7 pins. If the impedance of the signal source is high, connect capacitors with a high capacitance to the ANI0 to ANI7 pins. An example of this is shown in Figure 14-18. In this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a low-pass filter is created. To convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer.
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Figure 14-17. Internal Equivalent Circuit of Pins ANI0 to ANI7
R1 ANIn
R2
C1
C2
C3
Remark
n = 0 to 7
Table 14-3. Resistances and Capacitances of Equivalent Circuit (Reference Values)
AVREF0 1.8 V 2.7 V 4.5 V R1 75 k 12 k 4 k R2 30 k 8 k 2.7 k C1 8 pF 8 pF 8 pF C2 4 pF 3 pF 1.4 pF C3 2 pF 2 pF 2 pF
Caution
The resistances and capacitances in Table 14-3 are not guaranteed values.
Figure 14-18. Example of Connection If Signal Source Impedance Is High

Output impedance of sensor R0
ANIn
R1
R2
C1 C0 0.1 F Low-pass filter is created. C0
C2
C3
Remark
n = 0 to 7
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CHAPTER 15 D/A CONVERTER
15.1 D/A Converter Functions
The D/A converter converts a digital input into an analog value. The D/A converter used is a 2-channel 8-bit resolution voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start D/A conversion by setting bits 0 and 1 (DACE0 and DACE1) of the D/A converter mode register (DAM). There are two modes for the D/A converter, as follows. (1) Normal mode Outputs an analog voltage signal immediately after D/A conversion. (2) Real-time output mode Outputs an analog voltage signal synchronously with the output trigger after D/A conversion. Since a sine wave can be generated in this mode, it is useful for an MSK modem for cordless telephone sets.
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15.2 D/A Converter Configuration
The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration
Item Registers Configuration D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) D/A converter mode register (DAM)
Control register
Figure 15-1. D/A Converter Block Diagram
Internal bus
DACS1 write INTTM2 DACS0 Write INTTM1
D/A conversion value set register 1 (DACS1) D/A conversion value set register 0 (DACS0) 2R ANO1/P131 2R Selector 2R 2R 2R Selector 2R 2R R R R 2R ANO0/P130 R
AVREF1 AVSS
DAM5 DAM4 DACE1 DACE0 D/A converter mode register Internal bus
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(1) D/A conversion value set registers 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values used to determine the analog voltages to be output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with an 8-bit memory manipulation instruction. RESET input clears DACS0 and DACS1 to 00H. Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression. ANOn output voltage = AVREF1 x where, n = 0, 1 DACSn 256
Cautions 1. In the real-time output mode, when data that is set in DACS0 and DACS1 is read before an output trigger is generated, the previous data is read rather than the set data. 2. In the real-time output mode, data should be set to DACS0 and DACS1 after an output trigger and before the next output trigger.
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15.3 D/A Converter Control Registers
The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. DAM is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input clears DAM to 00H. Figure 15-2. Format of D/A Converter Mode Register
7 0 6 0 5 4 3 0 2 0 <1> <0> Address FF98H After reset 00H R/W R/W
Symbol DAM
DAM5 DAM4
DACE1 DACE0
DACE0 0 1 DACE1 0 1 DAM4 0 1 DAM5 0 1
D/A converter channel 0 control D/A conversion stop D/A conversion enable D/A converter channel 1 control D/A conversion stop D/A conversion enable D/A converter channel 0 operating mode Normal mode Real-time output mode D/A converter channel 1 operating mode Normal mode Real-time output mode
Cautions 1. When using the D/A converter, alternate-function port pins should be set to the input mode, and pull-up resistors should be disconnected. 2. Always set bits 2, 3, 6, and 7 to 0. 3. When D/A conversion is stopped, the output state is high-impedance. 4. The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1, respectively, in the real-time output mode.
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15.4 D/A Converter Operations
(1) The channel 0 operating mode and channel 1 operating mode are selected by bits 4 and 5 (DAM4 and DAM5), respectively, of the D/A converter mode register (DAM). (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively. (3) D/A conversion of channel 0 or channel 1 can be started by setting bits 0 or 1 (DACE0 or DACE1) of DAM, respectively. (4) In the normal mode, the analog voltage signals are output to the ANO0/P130 and ANO1/P131 pins immediately after D/A conversion. In the real-time output mode, the analog voltage signals are output synchronously with the output triggers. (5) In the normal mode, the analog voltage signals to be output are held until new data is set in DACS0 and DACS1. In the realtime output mode, new data is set in DACS0 and DACS1 and then held until the next trigger is generated. Caution Set DACE0 and DACE1 after setting data in DACS0 and DACS1.
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15.5 D/A Converter Cautions
(1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins. In addition, wiring from the ANOn pins to the buffer amplifier or the load should be as short as possible (because of high output impedance). If the wiring may be long, design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring. Figure 15-3. Use Example of Buffer Amplifier (a) Inverting amplifier
PD780058, 780058Y Subseries
C
R2 R1 ANOn
* The input impedance of the buffer amplifier is R1.
(b) Voltage-follower
PD780058, 780058Y Subseries
R ANOn R1 C
* The input impedance of the buffer amplifier is R1 . * If R1 is not connected, the output becomes undefined when RESET is low.
(2) Output voltage of D/A converter Because the output voltage of the converter changes in steps, use the D/A converter output signals in general by connecting a low-pass filter. (3) AVREF1 pin When only one of the D/A converter channels is used with AVREF1 < VDD0, the other pins that are not used as analog outputs must be set as follows: * * Set the PM13x bit of port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS0. Set the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, and output a low level from the pin. When not using the D/A converter, use AVREF1 with its potential the same as that of the VDD0.
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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
The PD780058 Subseries incorporates three serial interface channels. Differences between channels 0, 1, and 2 are as follows (see CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of serial interface channel 1 and CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of serial interface channel 2). Table 16-1. Differences Between Channels 0, 1, and 2
Serial Transfer Mode 3-wire serial I/O Clock selection fXX/2,
Channel 0 fXX/22, fXX/23, fXX/2, fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output
Channel 1 fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output MSB/LSB switchable as the start bit Automatic transmit/ receive function Serial transfer end interrupt request flag (CSIIF1) None
Channel 2 External clock, baud rate generator output
Transfer method
MSB/LSB switchable as the start bit
MSB/LSB switchable as the start bit
Transfer end flag
Serial transfer end interrupt request flag (CSIIF0) Use possible
Serial transfer end interrupt request flag (SRIF) None
SBI (serial bus interface) 2-wire serial I/O UART (Asynchronous serial interface)
None
Use possible Time-division transfer function
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16.1 Functions of Serial Interface Channel 0
Serial interface channel 0 employs the following four modes. * Operation stop mode * 3-wire serial I/O mode * SBI (serial bus interface) mode * 2-wire serial I/O mode Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface channel 0 is enabled to operate. To change the operating mode, stop the serial operation first. (1) Operation stop mode This mode is used when serial transfer is not carried out. Power consumption can be reduced in this mode. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) This mode is used for 8-bit data transfer using three lines, one each for the serial clock (SCK0), serial output (SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected regardless of their start bit recognition. This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate a conventional clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. (3) SBI (serial bus interface) mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using the serial clock (SCK0) and serial data bus (SB0 or SB1) lines (see Figure 16-1). The SBI mode conforms to the NEC Electronics serial bus format, and transmits or receives three types of transfer data: "addresses", "commands", and "data". * Address: * Data: Data to select the target device for serial communication Data actually transferred
* Command: Data to give an instruction to the target device
Actually, the master device outputs an "address" to the serial bus to select one of the slave devices with which the master device is to communicate. After that, "commands" and "data" are transmitted or received between the master and slave devices (this is the serial transfer). The receiver can automatically identify the received data as an "address", "command", or "data" by hardware. This function enables the I/O ports to be used effectively and the serial interface control portions of the application program to be simplified. In this mode, the wakeup function for handshake and the output function of acknowledge and busy signals can also be used.
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(4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using the two lines of the serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables support of any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in an increased number of available I/O ports. Figure 16-1. Serial Bus Interface (SBI) System Configuration Example
VDD0 Master CPU Slave CPU1
SCK0 SB0
SCK0 SB0
Slave CPU2
SCK0 SB0
Slave CPUn
SCK0 SB0
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16.2 Configuration of Serial Interface Channel 0
Serial interface channel 0 consists of the following hardware. Table 16-2. Configuration of Serial Interface Channel 0
Item Registers Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2)Note
Control registers
Note
See Figure 6-5 Block Diagram of P20, P21, and P23 to P26 and Figure 6-6 Block Diagram of P22 and P27.
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Figure 16-2. Block Diagram of Serial Interface Channel 0
Internal bus Serial bus interface control register
Slave address register (SVA)
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Serial operating mode register 0
CSIE0 COI WUP CSIM CSIM CSIM CSIM CSIM 04 03 02 01 00
SVAM Match
Controller SI0/SB0/ P25 PM25
Output control
Selector P25 Output latch Selector PM26
Output control
Serial I/O shift register 0 (SIO0)
CLR SET D Q
SO0/SB1/ P26
Bus release/ command/ acknowledge detector P26 Output latch Serial clock counter
Busy/ acknowledge output circuit ACKD CMDD RELD WUP Interrupt request signal generator TO2
CLD SCK0/ P27 PM27
Output control
INTCSI0
Serial clock controller CSIM00 CSIM01 P27 Output latch
Selector CSIM00 CSIM01
Selector
fXX/2 to fXX/28
4
CLD
SIC
SVAM
TCL33 TCL32 TCL31 TCL30
Interrupt timing specify register
Timer clock select register 3
Internal bus
Remark
The output control block performs selection between CMOS output and N-ch open-drain output.
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(1) Serial I/O shift register 0 (SIO0) SIO0 is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/ reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts a serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. Note that, if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pins must serve for both input and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address reception is carried out by setting bit 5 (WUP) of CSIM0 to 1). In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial bus interface control register (SBIC) is not cleared to 0. RESET input makes SIO0 undefined. (2) Slave address register (SVA) SVA is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus. The SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O mode. The master device outputs a slave address to the connected slave devices for selection of a particular slave device. These two data (the slave address output from the master device and the SVA value) are compared by an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked higher 7 bits by setting bit 4 (SVAM) of the interrupt timing specify register (SINT) to 1. If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. In the SBI mode, the wakeup function can be used by setting bit 5 (WUP) of CSIM0 to 1. In this case, the interrupt request signal (INTCSI0) is generated only when the slave address output by the master matches with the SVA value, and it can be learned by this interrupt request that the master requests communication. If bit 5 (SIC) of the interrupt timing specify register (SINT) is set to 1, the wakeup function cannot be used even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the wakeup function, clear SIC to 0. Further, an error can be detected by using SVA when the device transmits data as a master or slave device in the SBI or 2-wire serial I/O mode. RESET input makes SVA undefined.
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(3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. (5) Serial clock controller This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/P27 pin. (6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates an interrupt request signal in the following cases. * In the 3-wire serial I/O mode and 2-wire serial I/O mode This circuit generates an interrupt request signal every eight serial clocks. * In the SBI mode When WUP is 0 ........... Generates an interrupt request signal every eight serial clocks. When WUP is 1 ........... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0) value matches the slave address register (SVA) value after address reception. Remark WUP is the wakeup function specification bit. It is bit 5 of serial operating mode register 0 (CSIM0). When using the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. (7) Busy/acknowledge output circuit and bus release/command/acknowledge detector These two circuits output and detect various control signals in the SBI mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
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16.3 Control Registers of Serial Interface Channel 0
The following four registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specification register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H.
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Figure 16-3. Format of Timer Clock Select Register 3
Symbol 7 6 5 4 3 2 1 0 Address FF43H After reset 88H R/W R/W
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30
Serial interface channel 0 serial clock selection MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz)
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28
Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
Other than above
Setting prohibited
TCL37 TCL36 TCL35 TCL34
Serial interface channel 1 serial clock selection MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz)
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28
Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
Other than above
Setting prohibited
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS:Bit 0 of oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) Serial operating mode register 0 (CSIM0) This register sets the serial interface channel 0 serial clock, operating mode, operation enable/stop wakeup function and displays the address comparator match signal. CSIM0 is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H. Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface channel 0 is enabled to operate. To change the operating mode, stop the serial operation first. Figure 16-4. Format of Serial Operating Mode Register 0 (1/2)
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified by bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode 3-wire serial l/O mode SBI mode
Start bit
SI0/SB0/P25 pin function SI0Note 2 (input) P25 (CMOS I/O) SB0 (N-ch open-drain I/O)
SO0/SB1/P26 pin function SO0 (CMOS output) SB1 (N-ch open-drain I/O) P26 (CMOS I/O)
SCK0/P27 pin function SCK0 (CMOS I/O) SCK0 (CMOS I/O)
0
x
0 1
Note 2 Note 2
1
x
0
0
0
1
MSB LSB MSB
Note 3 Note 3
1
0
0
x
x
0
0
0
1
Note 3 Note 3
1
0
0
x
x
0
1
Note 3 Note 3
1
1
0
x
x
0
0
0
1
2-wire serial l/O mode
MSB
P25 (CMOS I/O)
SCK0 SB1 (N-ch (N-ch open-drain I/O) open-drain I/O) P26 (CMOS I/O)
Note 3 Note 3
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O)
(Cont'd) Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS I/O) when used only for transmission. 3. Can be used freely as a port function. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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Figure 16-4. Format of Serial Operating Mode Register 0 (2/2)
R/W WUP 0 1 Wakeup function controlNote 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
R
COI 0 1
Slave address comparison result flagNote 2 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. When using the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. 2. When CSIE0 = 0, COI becomes 0.
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(3) Serial bus interface control register (SBIC) This register sets the serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Figure 16-5. Format of Serial Bus Interface Control Register (1/2)
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/WNote
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
Used for bus release signal output. When RELT = 1, the SO0 Iatch is set to 1. After the SO0 latch is set, is RELT automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output. When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R
RELD Clear conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
Bus release detection Set conditions (RELD = 1) * When bus release signal (REL) is detected
R CMDD Clear conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied
Command detection Set conditions (CMDD = 1) * When command signal (CMD) is detected
R/W
ACKT
The acknowledge signal is output in synchronization with the falling edge of the SCK0 clock just after execution of the instruction that sets this bit to 1, and after acknowledge signal output, ACKT is automatically cleared to 0. ACKT is used with ACKE = 0. ACKT is also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
Note
Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting. 2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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Figure 16-5. Format of Serial Bus Interface Control Register (2/2)
R/W
ACKE 0 1
Acknowledge signal automatic output control Acknowledge signal automatic output disable (output by ACKT enabled) Before completion of transfer After completion of transfer The acknowledge signal is output in synchronization with the falling edge of the 9th SCK0 clock (automatically output when ACKE = 1). The acknowledge signal is output in synchronization with the falling edge of SCK0 just after execution of the instruction that sets this bit to 1 (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal is output.
R
ACKD Clear conditions (ACKD = 0)
Acknowledge detection Set conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of the SCK0 clock after completion of transfer
* Falling edge of SCK0 immediately after busy mode is released after executing the transfer start instruction * When CSIE0 = 0 * When RESET input is applied
Note
R/W
BSYE 0 1
Synchronizing busy signal output control Disable the busy signal which is output in synchronization with the falling edge the SCK0 clock just after execution of the instruction that clears this bit to 0. Output the busy signal at the falling edge of the SCK0 clock following the acknowledge signal.
Note
The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0.
Remark
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H. Figure 16-6. Format of Interrupt Timing Specification Register
Symbol SINT
7 0
<6> CLD
<5>
<4>
3 0
2 0
1 0
0 0
Address FF63H
After reset 00H
R/W R/WNote 1
SIC SVAM
R/W SVAM 0 1 R/W SIC 0 1 INTCSI0 interrupt source selectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer SVA bit to be used as slave address Bits 0 to 7 Bits 1 to 7
R CLD 0 1 Low level High level
SCK0/P27 pin levelNote 3
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wakeup function in the SBI mode, clear SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Caution Be sure to clear bits 0 to 3 to 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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16.4 Operations of Serial Interface Channel 0
The following four operating modes are available for serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * SBI mode * 2-wire serial I/O mode 16.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial I/O shift register 0 (SIO0) does not carry out shift operations either and thus it can be used as an ordinary 8-bit register. In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1, and P27/SCK0 pins can be used as ordinary I/O ports. (1) Register setting The operation stop mode is set by serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Symbol
<7>
<6>
<5> WUP
4
3
2
1
0
Address FF60H
After reset 00H
R/W R/W
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
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16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with the three lines of the serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set by serial operating mode register 0 (CSIM0) and the serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
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Symbol
<7>
<6>
<5> WUP
4
3
2
1
0
Address FF60H
After reset 00H
R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified by bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode 3-wire serial l/O mode
Start bit
SIO/SB0/P25 pin function SI0Note 2 (input)
SO0/SB1/P26 pin function SO0 (CMOS output)
SCK0/P27 pin function SCK0 (CMOS I/O)
0
x
0 1
Note 2 Note 2
1
x
0
0
0
1
MSB LSB
1 1
0 1
SBI mode (see 16.4.3 SBI mode operation.) 2-wire serial I/O mode (see 16.4.4 2-wire serial I/O mode operation.)
R/W
WUP 0 1
Wakeup function controlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register data in SBI mode
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Be sure to clear WUP to 0 when the 3-wire serial I/O mode is selected. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO0 Iatch is set to 1. After the SO0 Iatch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 16-7. 3-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0 End of transfer Transfer start at the falling edge of SCK0
The SO0 pin is a CMOS output pin and outputs the current SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (see 16.4.5 SCK0/P27 pin output manipulation). (3) Other signals Figure 16-8 shows the RELT and CMDT operations. Figure 16-8. RELT and CMDT Operations
SO0 latch
RELT
CMDT
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(4) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, it is possible to select transfer to start from the MSB or LSB. Figure 16-9 shows the configuration of serial I/O shift register 0 (SIO0) and the internal bus. As shown in the figure, the MSB/LSB can be read or written in reverse form. MSB/LSB switching as the start bit can be specified by bit 2 (CSIM02) of serial operating mode register 0 (CSIM0). Figure 16-9. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SO0 latch SI0 Serial I/O shift register 0 (SIO0) D Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO0. (5) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1. * Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer. Caution If CSIE0 is set to 1 after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set.
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16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface that complies with the NEC Electronics serial bus format. SBI uses a single master device and employs a clocked serial I/O format with the addition of a bus configuration function. This function enables devices to communicate using only two lines. Thus, when making up a serial bus with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on the board can be decreased. The master device outputs three kinds of data to slave devices on the serial data bus: "addresses" to select a device to be communicated with, "commands" to instruct the selected device, and "data" which is actually required. The slave device can identify the received data as "address", "command", or "data" by hardware. An application program that controls serial interface channel 0 can be simplified by using this function. The SBI function is incorporated into various devices including the 75X/XL Series and 78K Series. Figure 16-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used. In SBI, the SB0 (SB1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as a wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data bus line. When the SBI mode is used, see (11) SBI mode precautions (d) described later. Figure 16-10. Example of Serial Bus Configuration with SBI
VDD0
Serial clock SCK0 Master CPU Serial data bus SB0 (SB1) SB0 (SB1) Address 1 SCK0 Slave CPU
SCK0
Slave CPU
SB0 (SB1)
Address 2
* * *
* * *
SCK0
Slave IC
SB0 (SB1)
Address N
Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out asynchronously between the master and slave CPUs.
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(1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary to provide chip select signals to identify commands and data, and to judge the busy state, because only the data transfer function is available. If these operations are to be controlled by software, the software load becomes very heavy. In SBI, a serial bus can be configured with the two signal lines of the serial clock SCK0 and serial data bus SB0 (SB1). Thus, use of SBI leads to a reduction in the number of microcontroller ports and the amount of wiring and routing on the board. The SBI functions are described below. (a) Address/command/data identification function Serial data is distinguished as addresses, commands, and data. (b) Chip select function by address transmission The master executes slave chip selection by address transmission. (c) Wakeup function The slave can easily judge address reception (chip select judgment) using the wakeup function (which can be set/reset by software). When the wakeup function is set, the interrupt request signal (INTCSI0) is generated upon reception of a match address. Thus, when communication is executed with two or more devices, the CPU except the selected slave device can operate regardless of serial communications. (d) Acknowledge signal (ACK) control function The acknowledge signal used to check serial data reception is controlled. (e) Busy signal (BUSY) control function The busy signal used to report the slave busy state is controlled.
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(2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred by SBI consists of three kinds of data: "address", "command", and "data". Figure 16-11 shows the address, command, and data transfer timing. Figure 16-11. SBI Transfer Timing
Address transfer
SCK0
8
9
SB0 (SB1) Bus release signal
A7 Address Command signal
A0
ACK
BUSY
Command transfer
SCK0
9
SB0 (SB1)
C7 Command
C0 ACK
BUSY
READY
Data transfer
SCK0
8
9
SB0 (SB1)
D7 Data
D0 ACK
BUSY
READY
Remark
The broken lines indicate the READY status.
The bus release signal and the command signal are output by the master device. BUSY is output by the slave device. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs). Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
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(a) Bus release signal (REL) The bus release signal is recognized when the SB0 (SB1) line changes from low level to high level when the SCK0 line is at high level (without serial clock output). This signal is output by the master device. Figure 16-12. Bus Release Signal
SCK0 SB0 (SB1)
"H"
The bus release signal indicates that the master device is going to transmit an address to the slave device. The slave device incorporates hardware to detect the bus release signal. Caution The transition of the SB0 (SB1) line from low to high when the SCK0 line is high is recognized as a bus release signal. If the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release signal. Exercise care in wiring so that noise is not superimposed on the signal lines. (b) Command signal (CMD) The command signal is recognized when the SB0 (SB1) line changes from high level to low level when the SCK0 line is at high level (without serial clock output). This signal is output by the master device. Figure 16-13. Command Signal
SCK0 SB0 (SB1)
"H"
The command signal indicates that the master is going to transmit a command to the slave (however, a command signal following a bus release signal indicates that an address is transmitted). The slave device incorporates hardware to detect the command signal. Caution The transition of the SB0 (SB1) line from high to low when the SCK0 line is high is recognized as a command signal. If the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a command signal. Exercise care in wiring so that noise is not superimposed on the signal lines.
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(c) Address An address is 8-bit data which the master device outputs to the slave devices connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses
SCK0 SB0 (SB1)
1 A7
2 A6
3 A5
4 A4
5 A3
6 A2
7 A1
8 A0
Address Bus release signal Command signal
8-bit data following bus release and command signals is defined as an "address". In the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device has been selected. After that, communication with the master device continues until a release instruction is received from the master device. Figure 16-15. Slave Selection by Address
Master Slave 2 Address transmission
Slave 1
Not selected
Slave 2
Selected
Slave 3
Not selected
Slave 4
Not selected
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(d) Commands and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands
SCK0 SB0 (SB1) 1 C7 2 C6 3 C5 4 C4 5 C3 6 C2 7 C1 8 C0
Command signal
Command
Figure 16-17. Data
SCK0 SB0 (SB1) 1 D7 2 D6 3 D5 4 D4 Data 5 D3 6 D2 7 D1 8 D0
8-bit data following a command signal is defined as "command" data. 8-bit data without a command signal is defined as "data". Command and data operation procedures can be determined by the user according to their communication specifications.
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(e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between the transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th SCK0 clock]
SCK0 8 9 10 11
SB0 (SB1)
ACK
[When output in synchronization with 9th SCK0 clock]
SCK0 8 9
SB0 (SB1)
ACK
Remark
The broken lines indicate the READY status.
The acknowledge signal is one-shot pulse generated at the falling edge of SCK0 after 8-bit data transfer. It can be positioned anywhere and can be synchronized with any SCK0 clock. After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. If the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly.
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(f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is used to report to the master device that the slave device is not ready for data transmission/reception. The READY signal is used to report to the master device that the slave device is ready for data transmission/reception. Figure 16-19. BUSY and READY Signals
SCK0 8 9
SB0 (SB1)
ACK
BUSY
READY
In SBI, the slave device notifies the master device of the busy state by setting the SB0 (SB1) line to low level. BUSY signal output follows acknowledge signal output from the master or slave device. It is set/reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically terminates the output of the SCK0 serial clock. When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer. Caution In the SBI mode, the BUSY signal is output until the next serial clock (SCK0) falls after a command that resets the BUSY signal has been issued. If WUP is set to 1 during this period by mistake, the BUSY signal is not reset. Therefore, be sure to confirm that the SB0 (SB1) pin has gone high after resetting the BUSY signal, by setting WUP to 1.
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(3) Register setting The SBI mode is set by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode
Start bit
SI0/SB0/P25 pin function
SO0/SB1/P26 pin function
SCK0/P27 pin function
0 1
x 0
3-wire serial I/O mode (see 16.4.2 3-wire serial I/O mode operation.)
Note 2 Note 2
0
x
x
0
0
0
1
SBI mode
MSB
P25 (CMOS I/O)
SB1 (N-ch open-drain I/O) P26 (CMOS I/O)
SCK0 (CMOS I/O)
Note 2 Note 2
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O)
1
1
2-wire serial I/O mode (see 16.4.4 2-wire serial I/O mode operation.)
R/W
WUP 0 1
Wakeup function control
Note 3
Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
Note 4
R
COI 0 1
Slave address comparison result flag
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as a port function. 3. When using the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. 4. When CSIE0 = 0, COI becomes 0. Remark x: Pxx: don't care Port output latch
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/WNote
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
Used for bus release signal output. When RELT = 1, the SO0 Iatch is set to 1. After the SO0 latch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output. When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R
RELD Clear conditions (RELD = 0)
Bus release detection Set conditions (RELD = 1) * When bus release signal (REL) is detected
* When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception (only when WUP = 1) * When CSIE0 = 0 * When RESET input is applied
R CMDD Clear conditions (CMDD = 0) * When transfer start instruction is executed * When bus release signal (REL) is detected * When CSIE0 = 0 * When RESET input is applied
Command detection Set conditions (CMDD = 1) * When command signal (CMD) is detected
R/W
ACKT
The acknowledge signal is output in synchronization with the falling edge of the SCK0 clock just after execution of the instruction that sets this bit to 1 and, after acknowledge signal output, ACKT is automatically cleared to 0. ACKT is used with ACKE = 0. ACKT is also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R/W
ACKE 0 1
Acknowledge signal automatic output control Acknowledge signal automatic output disable (output by ACKT enabled) Before completion of transfer After completion of transfer The acknowledge signal is output in synchronization with the falling edge of the 9th SCK0 clock (automatically output when ACKE = 1). The acknowledge signal is output in synchronization with falling edge of the SCK0 clock just after execution of the instruction that sets this bit to 1 (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal output.
(Cont'd) Note Bits 2, 3, and 6 (RELD, CMDD and ACKD) are read-only bits.
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting. 2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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R
ACKD Clear conditions (ACKD = 0)
Acknowledge detection Set conditions (ACKD = 1) * When the acknowledge signal (ACK) is detected at the rising edge of the SCK0 clock after completion of transfer
* When SCK0 falls immediately after busy mode is released after transfer start instruction execution. * When CSIE0 = 0 * When RESET input is applied
R/W
Note
BSYE 0 1
Synchronizing busy signal output control Disable the busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction that clears this bit to 0 (set READY status). Output the busy signal at the falling edge of the SCK0 clock following the acknowledge signal.
Note
Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0.
Remark
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Symbol SINT 7 0 <6> CLD <5> <4> 3 0 2 0 1 0 0 0 Address FF63H After reset 00H R/W R/WNote 1
SIC SVAM
R/W SVAM 0 1 R/W SIC 0 1 SVA bit to be used as slave address Bits 0 to 7 Bits 1 to 7
INTCSI0 interrupt source selectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R CLD 0 1 Low level High level
SCK0/P27 pin levelNote 3
Caution Be sure to clear bits 0 to 3 to 0. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wakeup function in the SBI mode, clear SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master)
Slave address write to SIO0 (transfer start instruction) SIO0
SCK0
SB0 (SB1)
RELT
CMDT
RELD
CMDD
Figure 16-21. RELD and CMDD Operations (Slave)
Write FFH to SIO0 (transfer start instruction) SIO0 A7 A6 A1 A0
Transfer start instruction
SCK0
1
2
7
8
9 READY
SB0 (SB1)
A7
A6
A1
A0
ACK When addresses match
Slave address RELD
When addresses do not match CMDD
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Figure 16-22. ACKT Operation
SCK0 SB0 (SB1) ACKT
6 D2
7 D1
8 D0
9 ACK ACK signal is output for a period of one clock just after setting
If ACKT is set during this period
Caution Do not set ACKT before completion of transfer.
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Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer
SCK0 1 2 7 8 9
SB0 (SB1) ACKE
D7
D6
D2
D1
D0
ACK
ACK signal is output at 9th clock
When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
ACK signal is output for a period of one clock just after setting
ACKE
If ACKE is set during this period and it is still 1 at the falling edge of the next SCK0
(c) When ACKE = 0 upon completion of transfer
SCK0 SB0 (SB1) 1 D7 2 D6 D2 7 D1 8 D0 9 ACK signal is not output
ACKE
When ACKE = 0 at this point
(d) When ACKE = 1 period is short
SCK0 SB0 (SB1) D2 D1 D0 ACK signal is not output
ACKE
If ACKE is set and then cleared during this period and it is still 0 at the falling edge of SCK0
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Figure 16-24. ACKD Operations (a) When ACK signal is output at 9th SCK0 clock
Transfer Start Instruction SIO0 Transfer Start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after 9th SCK0 clock
Transfer start instruction SIO0 Transfer start SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
ACKD
(c) Clear timing when transfer start is instructed during BUSY
Transfer start instruction SIO0
SCK0
6
7
8
9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
D7
D6
ACKD
Figure 16-25. BSYE Operation
SCK0 6 7 8 9
SB0 (SB1)
D2
D1
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
If BSYE is reset during this period and it is still 0 at the falling edge of SCK0
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Table 16-3. Various Signals in SBI Mode (1/2)
Signal Name Bus release signal (REL) Output Device Master Definition SB0 (SB1) rising edge when SCK0 = 1 Timing Chart Output Conditions * RELT set Effects on Flag * RELD set * CMDD clear Meaning of Signal CMD signal is output to indicate that transmit data is an address. i) Transmit data is an address after REL signal output. ii) REL signal is not output and transmit data is an command. Completion of reception
SCK0 SB0 (SB1)
"H"
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Command signal (CMD)
Master
SB0 (SB1) falling edge when SCK0 = 1
* CMDT set
* CMDD set
SCK0 SB0 (SB1)
"H"
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
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Acknowledge signal (ACK)
Master/ slave
Low-level signal output to SB0 (SB1) during oneclock period of SCK0 after completion of serial reception [Synchronous BUSY signal] Low-level signal output to SB0 (SB1) following acknowledge signal
1 ACKE = 1 2 ACKT set
* ACKD set
[Synchronous BUSY output] * BSYE = 1 -- Serial receive disabled because of processing
Busy signal (BUSY)
Slave
SCK0 SB0 (SB1)
9
ACK BUSY
D0
ACK BUSY
READY
1 BSYE = 0 2 Execution of instruction for data write to SIO0 (transfer start instruction) -- Serial receive enabled
Ready signal (READY)
Slave
High-level signal output to SB0 (SB1) before serial transfer start and after completion of serial transfer
SB0 (SB1)
D0
READY
317
318
Signal Name Serial clock (SCK0) Output Device Master Definition Address (A7 to A0)
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Table 16-3. Various Signals in SBI Mode (2/2)
Timing Chart Output Conditions Effects on Flag Meaning of Signal
Synchronous clock to output address/command/data, SCK0 ACK signal, synchronous BUSY signal, etc. Address/ command/data is transferred SB0 (SB1) with the first eight synchronous clocks. 8-bit data transferred in SCK0 synchronization with SCK0 after output of REL and CMD signals SB0 (SB1)
1
2
7
8
9
10
When CSIE0 = 1, CSIIF0 set (rising Timing of signal edge of 9th clock output to serial data execution of bus of SCK0)Note 1 instruction for data write to SIO0 (serial transfer start instruction)Note 2 Address value of slave device on the serial bus
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Master
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
1
2
7
8
REL
CMD
Command (C7 to C0)
Master
8-bit data transferred in SCK0 synchronization with SCK0 after output of only CMD signal without REL signal SB0 (SB1) output 8-bit data transferred in synchronization with SCK0 without output of REL and CMD signals
1
2
7
8
Instructions and messages to the slave device
CMD
Data (D7 to D0)
Master/ slave
SCK0
1
2
7
8
Numeric values to be processed by slave or master device
SB0 (SB1)
Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set (if the address does not match the value of SVA, RELD is cleared). 2. In the BUSY state, transfer starts after the READY state is set.
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(5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 ............ Serial clock I/O pin 1 2 Master ... CMOS and push-pull output Slave ...... Schmitt input Both master and slave devices have an N-ch open-drain output and a Schmitt input. Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary. Figure 16-26. Pin Configuration
Slave device
(b) SB0 (SB1) .... Serial data I/O alternate-function pin
Master service (Clock output) Clock input Serial clock (Clock input) VDD0 RL Serial data bus VSS0 SI0 VSS0 SI0
SCK0 Clock output
SCK0
N-ch open-drain SO0
SB0 (SB1)
SB0 (SB1)
N-ch open-drain SO0
Caution Because the N-ch open-drain output must made to go into a high-impedance state during data reception, write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch open-drain output can always go into a high-impedance state during transfer. However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain output always goes into a highimpedance state. Thus, it is not necessary to write FFH to SIO0 before reception.
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(6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. A match of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master matches the address set to SVA when the wakeup function specification bit (WUP) = 1. If bit 5 (SIC) of the interrupt timing specify register (SINT) is set, the wakeup function cannot be used even if WUP is set (an interrupt request signal is generated when bus release is detected). To use the wake-up function, clear SIC to 0. Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after bus release (RELD = 1). For this match detection, the match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. detection by slave address when WUP = 1. 2. When detecting selection/non-selection without the use of an interrupt request with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) Error detection In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following ways. (a) Method of comparing SIO0 data before and after transmission In this case, if the two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred. (8) Communication operation In the SBI mode, the master device normally selects one slave device as the communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave device. Figures 16-27 to 16-30 show data communication timing charts. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0). Transmit data is latched into the SO0 latch and is output with the MSB set as the first bit from the SB0/P25 or SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into SIO0. Thus, execute selection/non-selection
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Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1)
Master device processing (transmitter) Program processing
CMDT set RELT set CMDT set
Write to SIO0
Interrupt servicing (preparation for the next serial transfer)
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Hardware operation
Serial transmission
INTCSI0
generation
ACKD set
SCK0 stop
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9
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SB0 (SB1) pin
A7
A6
A5
A4
A3
A2
A1
A0
ACK
BUSY
READY
Address Slave device processing (receiver) Program processing
WUP0 ACKT set BUSY clear
Hardware operation
CMDD CMDD CMDD set clear set RELD set
Serial reception
INTCSI0
generation
ACK BUSY output output
BUSY clear
(When SVA = SIO0)
321
322
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 pin
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Figure 16-28. Command Transmission from Master Device to Slave Device
CMDT set
Write to SIO0
Interrupt servicing (preparation for the next serial transfer)
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Serial transmission
INTCSI0
generation
ACKD set
SCK0 stop
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
1
2
3
4
5
6
7
8
9
SB0 (SB1) pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command Slave device processing (receiver) Program processing
SIO0 read
Command ACKT set analysis
BUSY clear
Hardware operation
CMDD set
Serial reception
INTCSI0
generation
ACK output
BUSY output
BUSY clear
Figure 16-29. Data Transmission from Master Device to Slave Device
Master device processing (transmitter) Program processing
Write to SIO0 Interrupt servicing (preparation for the next serial transfer)
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Hardware operation
Serial transmission
INTCSI0
generation
ACKD set
SCK0 stop
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9
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SB0 (SB1) pin
D7
D6
D5
D4
D3 Data
D2
D1
D0
ACK
BUSY
READY
Slave device processing (receiver) Program processing
SIO0 read ACKT set BUSY clear
Hardware operation
Serial reception
INTCSI0
generation
ACK output
BUSY output
BUSY clear
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324
Master device processing (receiver) Program processing Hardware operation Transfer line SCK0 pin
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Figure 16-30. Data Transmission from Slave Device to Master Device
FFH write to SIO0
SIO0 read
ACKT FFH Write to SIO0 set
Receive data processing
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SCK0 stop
Serial reception
INTCSI0
generation
ACK output
Serial reception
SERIAL INTERFACE CHANNEL 0 (PD780058 SUBSERIES)
1
2
3
4
5
6
7
8
9
1
2
SB0 (SB1) pin
BUSY
READY
D7
D6
D5
D4
D3 Data
D2
D1
D0
ACK
BUSY
READY
D7
D6
Slave device processing (transmitter) Program processing
Write to SIO0 Write to SIO0
Hardware operation
BUSY clear
Serial transmission
INTCSI0
generation
ACKD BUSY BUSY output set clear
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(9) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must go into a high-impedance state during data reception, write FFH to SIO0 in advance. However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain output always goes into a high-impedance state. Thus, it is not necessary to write FFH to SIO0 before reception. 3. If data is written to SIO0 when the slave is busy, the data is not lost. When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY) state, transfer starts. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. For pins that are to be used for data I/O, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> <2> <3> Set the P25 and P26 output latches to 1. Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. Reset the P25 and P26 output latches from 1 to 0.
(10) Judging busy state of slave When the device is in the master mode, follow the procedure below to judge whether the slave device is in the busy state or not. <1> Detect acknowledge signal (ACK) or interrupt request signal generation. <2> Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin to the input mode. <3> Read out the pin state (when the pin level is high, the READY state is set). After detection of the READY state, clear the port mode register to 0 and return to the output mode.
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(11) SBI mode precautions (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, the match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (b) When detecting selection/non-selection without the use of an interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) In the SBI mode, the BUSY signal is output until the next serial clock falls after a command that resets the BUSY signal has been issued. If WUP is set to 1 during this period by mistake, the BUSY signal is not reset. Therefore, be sure to confirm that the SB0 (SB1) pin has gone high after resetting the BUSY signal, by setting WUP to 1. (d) For pins that are to be used for data I/O, be sure to carry out the following settings before serial transfer of the 1st byte after RESET input. <1> Set the P25 and P26 output latches to 1. <2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. <3> Reset the P25 and P26 output latches from 1 to 0. (e) The transition of the SB0 (SB1) line from low to high or from high to low when the SCK0 line is high is recognized as a bus release signal or a command signal, respectively. If the transition timing of the bus is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release signal (or a command signal). Exercise care in wiring so that noise is not superimposed on the signal lines.
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16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with the two lines of the serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 16-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
VDD0 VDD0
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
(1) Register setting The 2-wire serial I/O mode is set by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
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Symbol
<7>
<6>
<5> WUP
4
3
2
1
0
Address FF60H
After reset 00H
R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode
Start bit
SIO/SB0/P25 pin function
SO0/SB1/P26 pin function
SCK0/P27 pin function
0 1 1
x 0 1
3-wire serial I/O mode (see 16.4.2 3-wire serial I/O mode operation) SBI mode (see 16.4.3 SBI mode operation)
Note 2 Note 2
0
x
x
0
0
0
1
2-wire serial l/O mode
MSB
P25 (CMOS I/O) SB0 (N-ch open-drain I/O)
SB1 SCK0 (N-ch (N-ch open-drain I/O) open-drain I/O) P26 (CMOS I/O)
Note 2 Note 2
1
0
0
x
x
0
1
R/W
WUP 0 1
Wakeup function controlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode Slave address comparison result flagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R
COI 0 1
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used freely as a port function. 3. Be sure to set WUP to 0 in the 2-wire serial I/O mode. 4. When CSIE0 = 0, COI becomes 0. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO0 Iatch is set to 1. After the SO0 Iatch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Symbol SINT 7 0 <6> CLD <5> <4> 3 0 2 0 1 0 0 0 Address FF63H After reset 00H R/W R/WNote 1
SIC SVAM
R/W SIC 0 1 INTCSI0 interrupt factor selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R CLD 0 1 Low level High level
SCK0/P27 pin levelNote 2
Caution Be sure to clear bits 0 to 3 to 0. Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Remark CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/ P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 16-32. 2-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SB0 (SB1)
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0 End of transfer Transfer start at the falling edge of SCK0
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally connected to a pull-up resistor. Because an N-ch open-drain output must go into a high-impedance state during data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (see 16.4.5 SCK0/P27 pin output manipulation).
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(3) Other signals Figure 16-33 shows the RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations
SO0 latch
RELT
CMDT
(4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to 1 after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must go into a high-impedance state during data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following ways. (a) Method of comparing SIO0 data before and after transmission In this case, if the two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred.
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16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (The SI0/SB0 and SO0/SB1 pins are controlled by bits 0 and 1 (RELT and CMDT) of the serial bus interface control register (SBIC).) The procedure for manipulating the SCK0/P27 pin output is described below. 1 2 Set serial operating mode register 0 (CSIM0) (SCK0 pin: Output mode, serial operation: Enabled). SCK0 = 1 while serial transfer is suspended. Manipulate the P27 output latch with a bit manipulation instruction. Figure 16-34. SCK0/P27 Pin Configuration
Manipulated by bit manipulation instruction SCK0/P27 To internal circuit P27 Output Latch SCK0 (1 while transfer is stopped) from serial clock controller When CSIE0 = 1 and CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
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CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (PD780058Y SUBSERIES)
The PD780058Y Subseries incorporates three serial interface channels. Differences between channels 0, 1, and 2 are as follows (see CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of serial interface channel 1 and CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of serial interface channel 2). Table 17-1. Differences Between Channels 0, 1, and 2
Serial Transfer Mode 3-wire serial I/O Clock selection
Channel 0 fXX/2, fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output MSB/LSB switchable as the start bit fXX/22, fXX/23,
Channel 1 fXX/2, fXX/24, fXX/25, fXX/26, fXX/27, fXX/28, external clock, TO2 output MSB/LSB switchable as the start bit Automatic transmit/ receive function Serial transfer end interrupt request flag (CSIIF1) None fXX/22, fXX/23,
Channel 2 External clock, baud rate generator output
Transfer method
MSB/LSB switchable as the start bit
Transfer end flag
Serial transfer end interrupt request flag (CSIIF0) Use possible
Serial transfer end interrupt request flag (SRIF) None
2-wire serial I/O I 2C bus (Inter IC Bus)
UART (Asynchronous serial interface)
None
Use possible Timer-division transfer function
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17.1 Functions of Serial Interface Channel 0
Serial interface channel 0 employs the following four modes. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface channel 0 is enabled to operate. To change the operating mode, stop the serial operation first. (1) Operation stop mode This mode is used when serial transfer is not carried out. Power consumption can be reduced in this mode. (2) 3-wire serial I/O mode (MSB-/LSB-first selectable) This mode is used for 8-bit data transfer using three lines, one each for the serial clock (SCK0), serial output (SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. The start bit of transferred 8-bit data is switchable between MSB and LSB, so that devices can be connected regardless of their start bit recognition. This mode should be used when connecting with peripheral I/O devices or display controllers which incorporate a conventional clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. (3) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available I/O ports.
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(4) I2C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using the two lines of the serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode complies with the I2C bus format. In this mode, the transmitter outputs three kinds of data onto the serial data bus: "start condition", "data", and "stop condition", to be actually sent or received. The receiver automatically distinguishes the received data as "start condition", "data", or "stop condition", by hardware. Figure 17-1. Serial Bus Configuration Example Using I2C Bus
VDD0 Master CPU
VDD0 Slave CPU1
SCL SDA0 (SDA1)
SCL SDA0 (SDA1)
Slave CPU2
SCL SDA0 (SDA1)
Slave CPUn
SCL SDA0 (SDA1)
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17.2 Configuration of Serial Interface Channel 0
Serial interface channel 0 consists of the following hardware. Table 17-2. Configuration of Serial Interface Channel 0
Item Registers Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specify register (SINT) Port mode register 2 (PM2)Note
Control registers
Note
See Figure 6-7 Block Diagram of P20, P21, and P23 to P26 and Figure 6-8 Block Diagram of P22 and P27.
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Figure 17-2. Block Diagram of Serial Interface Channel 0
Internal bus Serial bus interface control register
Slave address register (SVA)
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Serial operating mode register 0
CSIE0 COI WUP CSIM CSIM CSIM CSIM CSIM 04 03 02 01 00
SVAM Match BSYE
Controller SI0/SB0/ SDA0/P25 PM25
Output control
Selector P25 Output latch Selector PM26
Output control
Serial I/O shift register 0 (SIO0)
CLR SET D Q
SO0/SB1/ SDA1/P26
Acknowledge output circuit Stop condition/ start condition/ acknowledge detector ACKD CMDD RELD WUP Interrupt request signal generator TO2
CLD SCK0/ SCL/P27 PM27
Output control
P26 Output latch Serial clock counter Serial clock controller CSIM00 CSIM01 P27 Output latch
CLD SIC
INTCSI0
Selector
1/16 Divider
2
Selector
fXX/2 to fXX/28
CSIM00 CSIM01
4
SVAM CLC WREL WAT1 WAT0
TCL33 TCL32 TCL31 TCL30
Interrupt timing specify register
Timer clock select register 3
Internal bus
Remark
The output control block performs selection between CMOS output and N-ch open-drain output.
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(1) Serial I/O shift register 0 (SIO0) SIO0 is an 8-bit register used to carry out parallel-serial conversion and to carry out serial transmission/ reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts a serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. Note that, if a bus is driven in the I2C bus mode or 2-wire serial I/O mode, the bus pins must serve for both input and output. Therefore, the transmission N-ch transistor of the device which will start reception of data must be turned off beforehand. Consequently, write FFH to SIO0 in advance. In the I2C bus mode, set SIO0 to FFH with bit 7 (BSYE) of the serial bus interface control register (SBIC) set to 1. RESET input makes SIO0 undefined. Caution Do not execute an instruction that writes SIO0 in the I2C bus mode while WUP (bit 5 of serial operating mode register 0 (CSIM0)) = 1. Even if such an instruction is not executed, data can be received when the wake-up function is used (WUP = 1). For the detail of the wakeup function, see 17.4.4 (1) (c) Wake-up function. (2) Slave address register (SVA) SVA is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus. SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O mode. The master device outputs a slave address to the connected slave devices for selection of a particular slave device. These two data (the slave address output from the master device and the SVA value) are compared with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of LSB-masked higher 7 bits by setting bit 4 (SVAM) of the interrupt timing specify register (SINT) to 1. If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. In the I2C bus mode, the wakeup function can be used by setting bit 5 (WUP) of CSIM0 to 1. In this case, the interrupt request signal (INTCSI0) is generated when the slave address output by the master matches the SVA value (the interrupt request signal is also generated when the stop condition is detected), and it can be learned by this interrupt request that the master requests for communication. To use the wakeup function, set SIC to 1. Further, an error can be detected by using SVA when the device transmits data as a master or slave device in I2C bus mode or 2-wire serial I/O mode. RESET input makes SVA undefined. (3) SO0 latch This latch holds the SI0/SB0/SDA0/P25 and SO0/SB1/SDA1/P26 pin levels. It can be directly controlled by software. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received.
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(5) Serial clock controller This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/SCL/P27 pin. (6) Interrupt signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 17-3. (7) Acknowledge output circuit and stop condition/start condition/acknowledge detector These two circuits output and detect various control signals in the I2C mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode. Table 17-3. Interrupt Request Signal Generation of Serial Interface Channel 0
Serial Transfer Mode 3-wire or 2-wire serial I/O mode BSYE 0 WUP 0 WAT1 WAT0 ACKE 0 0 0 Description An interrupt request signal is generated each time 8 serial clocks are counted. Setting prohibited 0 0 An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). Normally, during transmission the settings WAT21, WAT0 = 1, 0, are not used. They are used only when wanting to coordinate receive time and processing systematically using software. ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable). An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ACK information is generated by the receiving side, thus ACKE should be set to 0 (disable). Setting prohibited 0 0 An interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ACK information is output by manipulating ACKT by software after an interrupt request is generated. 1 1 0/1 An interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). To automatically generate ACK information, preset ACKE to 1 before transfer start. However, in the case of the master, set ACKE to 0 (disable) before receiving the last data. After an address is received, if the values of serial I/ O shift register 0 (SI00) and the slave address register (SVA) match, and if the stop condition is detected, an interrupt request signal is generated. To automatically generate ACK information, preset ACKE to 1 (enable) before transfer start. Setting prohibited
Other than above I2C bus mode (transmit) 0 0 1
1
1
0
Other than above I2C bus mode (receive) 1 0 1
1
1
1
1
1
Other than above
Remark
BSYE: Bit 7 of the serial bus interface control register (SBIC) ACKE: Bit 5 of the serial bus interface control register (SBIC)
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17.3 Control Registers of Serial Interface Channel 0
The following four registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specification register (SINT) (1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H.
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Figure 17-3. Format of Timer Clock Select Register 3
Symbol 7 6 5 4 3 2 1 0 Address FF43H After reset 88H R/W R/W
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30
Serial interface channel 0 serial clock selection Serial clock in I2C bus mode MCS = 1 MCS = 0 fX/2 (78.1 kHz)
6
Serial clock in 2-wire or 3-wire serial I/O mode MCS = 1 fXX/2 fXX/22 fXX/23 fXX/24 Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) MCS = 0 fX/2 (1.25 MHz)
2
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fXX/2
5
Setting prohibited fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz)
fXX/26 fXX/27 fXX/28 fXX/29
fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.77 kHz)
fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz)
fX/210 (4.88 kHz) fXX/25
fXX/210 fX/210 (4.88 kHz) fX/211 (2.44 kHz) fXX/26 fXX/211 fX/211 (2.44 kHz) fX/212 (1.22 kHz) fXX/27 fXX/212 fX/212 (1.22 kHz) fX/213 (0.61 kHz) fXX/28 Setting prohibited
Other than above
TCL37 TCL36 TCL35 TCL34
Serial interface channel 1 serial clock selection MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz)
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28
Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
Other than above
Setting prohibited
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS: Bit 0 of oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz.
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(2) Serial operating mode register 0 (CSIM0) This register sets the serial interface channel 0 serial clock, operating mode, operation enable/stop wakeup function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H. Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface channel 0 is enabled to operate. To change the operating mode, stop the serial operation first. Figure 17-4. Format of Serial Operating Mode Register 0
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0/SCL pin from off-chip 8-bit timer register 2 (TM2) output Note 2 Clock specified by bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1 R/W
x 0 1
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode 3-wire serial l/O mode
Start Bit MSB LSB MSB
SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27 P25 pin function P26 pin function pin function SI0Note 3 (Input) P25 (CMOS I/O) SO0 (CMOS output) SCK0 (CMOS I/O)
0
x
0 1
Note 3 Note 3
1
x
0
0
0
1
Note 4 Note 4
1
1
0
x
x
0
0
0
Note 4 Note 4
1
0
0
x
x
0
1 2-wire serial l/O mode or I2C bus mode 1
SB1/SDA1 SCK0/SCL (N-ch (N-ch open-drain I/O) open-drain I/O) P26 (CMOS I/O)
SB0/SDA0 (N-ch open-drain
R/W
WUP 0 1
Wake-up function controlNote 5 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode
Note 6
R
COI 0 1
Slave address comparison result flag
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data Serial interface channel 0 operation control Operation stopped Operation enabled
R/W
CSIE0 0 1
Notes 1. 2. 3. 4. 5.
Bit 6 (COI) is a read-only bit. In I2C bus mode, the clock frequency becomes 1/16 of that output from TO2. Can be used as P25 (CMOS input/output) when used only for transmission. Can be used freely as a port function. To use the wakeup function (WUP = 1), set bit 5 (SIC) of the interrupt timing specification register (SINT) to 1. Do not execute an instruction that writes serial I/O shift register 0 (SIO0) while WUP = 1. 6. When CSIE0 = 0, COI becomes 0. x: don't care PMxx: Port mode register Pxx: Port output latch
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(3) Serial bus interface control register (SBIC) This register sets the serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Figure 17-5. Format of Serial Bus Interface Control Register (1/2)
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/WNote
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
Used for stop condition signal output. When RELT = 1, the SO0 Iatch is set to 1. After the SO0 latch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for start condition signal output. When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R
RELD Clear conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
Stop condition detection Set conditions (RELD = 1) * When stop condition signal is detected
R CMDD Clear conditions (CMDD = 0) * When transfer start instruction is executed * When stop condition signal is detected * When CSIE0 = 0 * When RESET input is applied
Start condition detection Set conditions (CMDD = 1) * When start condition signal is detected
R/W
ACKT
Used to generate the ACK signal by software when 8-clock wait mode is selected. Keeps SDA0 (SDA1) low from set instruction (ACKT = 1) execution to the next falling edge of SCL. ACKT is also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
Remark
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Figure 17-5. Format of Serial Bus Interface Control Register (2/2)
R/W ACKE 0 Acknowledge signal output controlNote 1 Acknowledge signal automatic output disable (However, output by ACKT enabled) Used for reception when 8-clock wait mode is selected or for transmission. Note 2 Enables acknowledge signal automatic output. Outputs the acknowledge signal in synchronization with the falling edge of 9th SCL clock cycle the (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal is output. Used in reception with 9-clock wait mode selected.
1
R
ACKD Clear conditions (ACKD = 0) * While executing the transfer start instruction * When CSIE0 = 0 * When RESETinput is applied
Acknowledge detection Set conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of the SCL clock after completion of transfer
R/W
Note 3
BSYE 0 1
Control of N-ch open-drain output for transmission in I2C Bus ModeNote 4 Output enabled (transmission) Output disabled (reception)
Notes 1. Setting should be performed before transfer. 2. If 8-clock wait mode is selected, the acknowledge signal at reception must be output using ACKT. 3. The busy mode can be cleared by start of serial interface transfer or reception of address signal. However, the BSYE flag is not cleared to 0. 4. When using the wakeup function, be sure to set BSYE to 1. Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H. Figure 17-6. Format of Interrupt Timing Specification Register (1/2)
Symbol SINT
7 0
<6> CLD
<5>
<4>
<3>
<2>
1
0
Address FF63H
After reset 00H
R/W R/WNote 1
SIC SVAM CLC WREL WAT1 WAT0
R/W
WAT1 WAT0 0 0
Wait and interrupt control Generates interrupt servicing request at rising edge of 8th SCK0 clock cycle (keeping clock output in high impedance). Setting prohibited Used in I2C bus mode (8-clock wait). Generates interrupt servicing request at rising edge of 8th SCK0 clock cycle. (In the case of master device, makes SCL output low to enter wait state after 8 clock pulses are output. In the case of slave device, makes SCL output low to request wait state after 8 clock pulses are input.) Used in I2C bus mode (9-clock wait). Generates interrupt servicing request at rising edge of 9th SCK0 clock cycle. (In the case of master device, makes SCL output low to enter wait state after 9 clock pulses are output. In the case of slave device, makes SCL output low to request wait state after 9 clock pulses are input.)
0 1
1 0
1
1
R/W
WREL 0 1 Wait state has been released.
Wait sate release control
Release wait state. Automatically cleared to 0 when the state is released (Used to cancel wait state by means of WAT0 and WAT1.)
R/W
CLC 0
Clock level controlNote 2 Used in I2C bus mode. Make output level of SCL pin low unless serial transfer is being performed. Used in I2C bus mode. Make SCL pin enter high-impedance state unless serial transfer is being performed (except for clock line which is kept high). Used to enable master device to generate start condition and stop condition signals.
1
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When not using the I2C mode, clear CLC to 0.
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Figure 17-6. Format of Interrupt Timing Specification Register (2/2)
R/W
SVAM 0 1 Bits 0 to 7 Bits 1 to 7
SVA bit to be used as slave address
R/W
SIC 0 1
INTCSI0 interrupt source selection Note 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer
R
CLD 0 1 Low level High level
SCK0/SCL pin levelNote 2
Notes 1. When using the wakeup function in the I2C mode, clear SIC to 0. 2. When CSIE0 = 0, CLD becomes 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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17.4 Operations of Serial Interface Channel 0
The following four operating modes are available for serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * I2C (Inter IC) bus mode 17.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial I/O shift register 0 (SIO0) does not carry out shift operations either and thus it can be used as an ordinary 8-bit register. In the operation stop mode, the P25/SI0/SB0/SDA0, P26/SO0/SB1/SDA1, and P27/SCK0/SCL pins can be used as general I/O ports. (1) Register setting The operation stop mode is set by serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Symbol
<7>
<6>
<5> WUP
4
3
2
1
0
Address FF60H
After reset 00H
R/W R/W
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
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17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with the three lines of the serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set by serial operating mode register 0 (CSIM0) and the serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Note 2 Note 2
Operation mode 3-wire serial l/O mode
Start bit MSB LSB
SIO/SB0/SDA0 SO0/SB1/SDA1 /P25 pin function /P26 pin function SI0Note 2 (input) SO0 (CMOS output)
SCK0/SCL/P27 pin function SCK0 (CMOS I/O)
0 1
x 1
0 1
1
x
0
0
0
1
2-wire serial I/O mode (see 17.4.3 2-wire serial I/O mode operation.) or 2 2 I C bus mode (see 17.4.4 I C bus mode operation.)
R/W
WUP 0 1
Wake-up function controlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input/output) when used only for transmission. 3. Be sure to clear WUP to 0 when the 3-wire serial I/O mode is selected. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO0 Iatch is set to 1. After the SO0 Iatch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 17-7. 3-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0 End of transfer Transfer start at the falling edge of SCK0
The SO0 pin is a CMOS output pin and outputs the current SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (see 17.4.8 SCK0/SCL/P27 pin output manipulation). (3) Other signals Figure 17-8 shows RELT and CMDT operations. Figure 17-8. RELT and CMDT Operations
SO0 latch
RELT
CMDT
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(4) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, it is possible to select transfer to start from the MSB or LSB. Figure 17-9 shows the configuration of serial I/O shift register 0 (SIO0) and the internal bus. As shown in the figure, the MSB/LSB can be read or written in reverse form. MSB/LSB switching as the start bit can be specified by bit 2 (CSIM02) of serial operating mode register 0 (CSIM0). Figure 17-9. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SO0 latch SI0 Serial I/O shift register 0 (SIO0) D Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to SIO0. (5) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1. * Internal serial clock is stopped or SCK0 is a high level after 8-bit serial transfer. Caution If CSIE0 is set to 1 after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set.
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17.4.3
2-wire serial I/O mode operation
The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with the two lines of the serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 17-10. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
VDD0 VDD0
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
(1) Register setting The 2-wire serial I/O mode is set by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
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Symbol
<7>
<6>
<5> WUP
4
3
2
1
0
Address FF60H
After reset 00H
R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 CSIM00
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified by bits 0 to 3 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02
Operation mode
Start bit
SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL/P27 /P25 pin function /P26 pin function pin function
0 1
x 1
3-wire serial I/O mode (see 17.4.2 3-wire serial I/O mode operation)
Note 2 Note 2
0
x
x
0
0
0
1
Note 2 Note 2
2-wire serial l/O mode or I2C bus mode
MSB
P25 (CMOS I/O) SB0/SDA0 (N-ch open-drain I/O)
SB1/SDA1 (N-ch open-drain I/O P26 (CMOS I/O)
SCK0/SCL (N-ch open-drain I/O)
1
0
0
x
x
0
1
R/W
WUP 0 1
Wakeup function controlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition (when CMDD = 1) matches the slave address register (SVA) data in I2C bus mode
R
COI 0 1
Slave address comparison result flagNote 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W
CSIE0 0 1 Operation stopped Operation enabled
Serial interface channel 0 operation control
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used freely as port function. 3. Be sure to clear WUP to 0 when the 2-wire serial I/O mode. 4. When CSIE0 = 0, COI becomes 0. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO0 Iatch is set to 1. After the SO0 Iatch is set, RELT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO0 Iatch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Symbol SINT
7 0
<6> CLD
<5>
<4>
<3>
<2>
1
0
Address FF63H
After reset 00H
R/W R/WNote 1
SIC SVAM CLC WREL WAT1 WAT0
R/W
SIC 0 1
INTCSI0 interrupt source selection CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon bus release detection or termination of serial interface channel 0 transfer
R
CLD 0 1 Low level High level
SCK0 pin levelNote 2
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Be sure to clear bits 0 to 3 to 0 in the 2-wire serial I/O mode is used. Remark CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/SDA0/P25 (or SB1/SDA1/P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into the SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 17-11. 2-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SB0 (SB1)
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0 End of Transfer Transfer Start at the Falling Edge of SCK0
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. Because N-ch open-drain output must go into a high-impedance state during data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (see 17.4.8 SCK0/SCL/P27 pin output manipulation).
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(3) Other signals Figure 17-12 shows the RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations
SO0 latch
RELT
CMDT
(4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to 1 after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must go into a high-impedance state during data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following way. (a) Method of comparing SIO0 data before transmission to that after transmission In this case, if two data differ from each other, a transmit error is judged to have occurred. (b) Method of using the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred.
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17.4.4
I2C bus mode operation
The I2C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allow the master device to communicate with a number of (slave) devices using only two lines: a serial clock (SCL) line and serial data bus (SDA0 or SDA1) line. Consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. In the I2C bus specification, the master sends start condition, data, and stop condition signals to slave devices via the serial data bus, while slave devices automatically detect and distinguish the type of signals using a signal detection function incorporated as hardware. The application program that controls the I2C bus can be simplified by using this function. An example of a serial bus configuration is shown in Figure 17-13. This system below is composed of CPUs and peripheral ICs having serial interface hardware that complies with the I2C bus specification. Note that pull-up resistors are required to connect to both the serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus. The signals used in the I2C bus mode are described in Table 17-4. Figure 17-13. Example of Serial Bus Configuration Using I2C Bus
VDD0 VDD0 Master CPU Serial clock Serial data bus Slave CPU1
SCL SDA0 (SDA1)
SCL SDA0 (SDA1)
Slave CPU2
SCL SDA0 (SDA1)
Slave IC
SCL SDA
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(1) I2C bus mode functions In the I2C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identify start condition, data, and stop condition signals sent in series via the serial data bus. (b) Chip selection by specifying device addresses The master device can select a specific slave device connected to the I2C bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) Wakeup function When address data is sent from the master device, slave devices compare it with the value registered in their internal slave address registers. If the values in one of the slave devices match, the slave device internally generates an interrupt request signal to terminate the current processing and communicates with the master device (the interrupt request also occurs when the stop condition is detected). Therefore, CPUs other than the selected slave device on the I2C bus can perform independent operations during the serial communication. (d) Acknowledge signal (ACK) control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) Wait signal (WAIT) control function When a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status.
(2) I2C bus definition This section describes the format of serial data communications and functions of the signals used in the I2C bus mode. First, the transfer timing of the "start condition", "data", and "stop condition" signals, which are output onto the signal data bus of the I2C bus, is shown in Figure 17-14. Figure 17-14. I2C Bus Serial Data Transfer Timing
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
SDA0 (SDA1) Start Address condition R/W ACK Data ACK Data ACK Stop condition
The start condition, slave address, and stop condition signals are output by the master. The acknowledge signal (ACK) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). A serial clock (SCL) is continuously supplied from the master device.
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(a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer. See 17.4.5 Cautions on Use of I2C Bus Mode, for details of the start condition output. The start condition signal is detected by hardware incorporated in slave devices. Figure 17-15. Start Condition
H SCL
SDA0 (SDA1)
(b) Address The 7 bits following the start condition signal are defined as an address. The 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. Each slave device on the bus line must therefore have a different address. Therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (SVA). After the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. Figure 17-16. Address
SCL
1
2
3
4
5
6
7
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
Address
(c) Transfer direction specification The 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. If this bit is 0, it is the master device which will send data to the slave. If it is 1, it is the slave device which will send data to the master. Figure 17-17. Transfer Direction Specification
SCL
1
2
3
4
5
6
7
8
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
Transfer direction specification
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(d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the transmitting side and receiving side devices for confirmation of correct data transfer. In principle, the receiving side device returns an acknowledge signal to the transmitting device each time it receives 8-bit data. The only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. The transmitting side that has transferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. If the transmitting side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. If this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. Figure 17-18. Acknowledge Signal
SCL
1
2
3
4
5
6
7
8
9
SDA0 (SDA1)
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
(e) Stop condition If the SDA0 (SDA1) pin level changes from low to high while the SCL pin is high, this transition is defined as a stop condition signal. The stop condition signal is output from the master to the slave device to terminate a serial transfer. The stop condition signal is detected by hardware incorporated in the slave device. Figure 17-19. Stop Condition
H SCL
SDA0 (SDA1)
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(f)
Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in a wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers. When the wait state is released, the master device can start the next transfer. For the releasing operation of slave devices, see 17.4.5 Cautions on Use of I2C Bus Mode. Figure 17-20. Wait Signal (a) Wait of 8 clock cycles
Set low because slave device drives low, though master device returns to Hi-Z state. No wait is inserted after 9th clock cycle (and before master device starts next transfer). SCL of master device SCL of slave device
6 7 8 9 1 2 3 4
SCL
SDA0 (SDA1)
D2
D1
D0
ACK
D7
D6
D5
D4
Output by manipulating ACKT
(b) Wait of 9 clock cycles
Set low because slave device drives low, though master device returns to Hi-Z state. SCL of master device SCL of slave device SCL 6 7 8 9 1 2 3
SDA0 (SDA1)
D2
D1
D0
ACK
D7
D6
D5
Output based on the value set in ACKE in advance
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(3) Register setting The I 2C mode setting is performed by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIM01 0 1 1
CSIM00 x 0 1
Serial interface channel 0 clock selection Input clock from off-chip to SCL pin 8-bit timer register 2 (TM2) outputNote 2 Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) P25 PM26 P26 PM27 P27 Operation mode Start bit SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27 P25 pin function P26 pin function pin function P25 (CMOS I/O) SB0/SDA0 N-ch opendrain I/O SB1/SDA1 N-ch opendrain I/O P26 (CMOS I/O) SCK0/SCL N-ch opendrain I/O SCK0/SCL N-ch opendrain I/O
R/W
CSIM CSIM CSIM PM25 04 03 02 0 1 x 1 0 x
Note 3
3-wire serial I/O mode (see 17.4.2 Operation in 3-wire serial I/O mode) x
Note 3
0
0
0
1
2-wire MSB serial I/O or I2C bus mode 2-wire MSB serial I/O or I2C bus mode
1
1
1
0
0
Note 3 Note 3
x
x
0
1
R/W
WUP 0 1
Wake-up function controlNote 4 Interrupt request signal generation with each serial transfer in any mode In I2C bus mode, interrupt request signal is generated when the address data received after start condition detection (when CMDD = 1) matches data in slave address register (SVA). Slave address comparison result flagNote 5 Slave address register (SVA) not equal to data in serial I/O shift register 0 (SIO0) Slave address register (SVA) equal to data in serial I/O shift register 0 (SIO0) Serial interface channel 0 operation control Operation stopped. Operation enabled.
R
COI 0 1
R/W
CSIE0 0 1
Notes 1. Bit 6 (COI) is a read-only bit. 2. In the I2C bus mode, the clock frequency is 1/16 of the clock frequency output by TO2. 3. Can be used freely as a port. 4. To use the wakeup function (WUP = 1), set bit 5 (SIC) of the interrupt timing specification register (SINT) to 1. Do not execute an instruction that writes serial I/O shift register 0 (SIO0) while WUP = 1. 5. When CSIE0 = 0, COI is 0. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H.
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/WNote 1
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W R/W R
RELT CMDT RELD 0
Use for stop condition output. When RELT = 1, the SO0 latch is set to 1. After the SO0 latch is set, RELT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. Use for start condition output. When CMDT = 1, the SO0 latch is cleared to 0. After the SO0 latch is cleared, CMDT is automatically cleared to 0. It is also cleared to 0 when CSIE0 = 0. Stop condition detection Clear conditions * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied Setting condition * When stop condition is detected Start condition detection Clear conditions * When transfer start instruction is executed * When stop condition is detected * When CSIE0 = 0 * When RESET input is applied Setting condition * When start condition is detected SDA0 (SDA1) is set to low after the Set instruction execution (ACKT = 1) before the next SCL falling edge. Used for generating an ACK signal by software if the 8-clock wait mode is selected. Cleared to 0 if CSIE0 = 0 when a transfer by the serial interface is started. Acknowledge signal automatic output controlNote 2 Disabled (with ACKT enabled). Used when receiving data in the 8-clock wait mode or when transmitting data.Note 3 Enabled. After completion of transfer, the acknowledge signal is output in ACKE is synchronization with the 9th falling edge of the SCL clock (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal is output. It is used for reception when the 9-clock wait mode is selected. Acknowledge detection Clear Conditions * When transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied Set Conditions * When the acknowledge signal is detected at the rising edge of SCL clock after completion of transfer Control of N-ch open-drain output for transmission in I2C bus modeNote 5 Output enabled (transmission) Output disabled (reception)
1 R CMDD 0
1
R/W
ACKT
R/W
ACKE 0 1
R
ACKD 0
1
Note 4
R/W
BSYE 0 1
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, ACKD) are read-only bits. 2. This setting must be performed prior to transfer start. 3. In the 8-clock wait mode, use ACKT for output of the acknowledge signal after normal data reception. 4. The busy mode can be released by the start of a serial interface transfer or reception of an address signal. However, the BSYE flag is not cleared. 5. When using the wakeup function, be sure to set BSYE to 1. Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Symbol SINT 7 0 <6> CLD <5> SIC <4> <3> <2> 1 0 Address FF63H After reset 00H R/W R/WNote 1
SVAM CLC WREL WAT1 WAT0
R/W
WAT1 0 0 1
WAT0 0 1 0
Interrupt control by waitNote 2 Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output is high impedance). Setting prohibited Used in I2C bus mode (8-clock wait) Generates an interrupt service request on rise of 8th SCL clock cycle. (In case of master device, SCL pin is driven low after output of 8 clock cycles, to enter the wait state. In case of slave device, SCL pin is driven low after input of 8 clock cycles, to require the wait state.) Used in I2C bus mode (9-clock wait) Generates an interrupt service request on rise of 9th SCL clock cycle. (In case of master device, SCL pin is driven low after output of 9 clock cycles, to enter the wait state. In case of slave device, SCL pin is driven low after input of 9 clock cycles, to require the wait state.) Wait release control
1
1
R/W
WREL 0 1
Indicates that the wait state has been released. Releases the wait state. Automatically cleared to 0 after releasing the wait state. This bit is used to release the wait state set by means of WAT0 and WAT1. Clock level control Used in I2C bus mode. In cases other than serial transfer, SCL pin output is driven low. Used in I2C bus mode. In cases other than serial transfer, SCL pin output is set to high impedance. (Clock line is held high.) Used by master device to generate the start condition and stop condition signals. SVA bits used as slave address Bits 0 to 7 Bits 1 to 7 INTCSI0 interrupt source selectionNote 3 CSIIF0 is set to 1 after end of serial interface channel 0 transfer. CSIIF0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected. SCL pin levelNote 4 Low level High level
R/W
CLC 0 1
R/W
SVAM 0 1
R/W
SIC 0 1
R
CLD 0 1
Notes 1. Bit 6 (CLD) is read-only. 2. When the I2C bus mode is used, be sure to set WAT0 and WAT1 to 1 and 0, or 1 and 1, respectively. 3. When using the wakeup function in I2C mode, be sure to set SIC to 1. 4. When CSIE0 = 0, CLD is 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Various signals A list of signals in the I2C bus mode is given in Table 17-4. Table 17-4. Signals in I2C Bus Mode
Signal name Start condition Definition: Function: Signaled by: Signaled when: Affected flag(s): Stop condition Definition: Function: Signaled by: Signaled when: Affected flag(s): Acknowledge signal (ACK) Definition: Function: Signaled by: Signaled when: Affected flag(s): Wait (WAIT) Definition: Function: Signaled by: Signaled when: Affected flag(s): Serial clock (SCL) Definition: Function: Signaled by: Signaled when: Affected flag(s): Address (A6 to A0) Definition: Function: Signaled by: Signaled when: Affected flag(s): Transfer direction (R/W) Definition: Function: Signaled by: Signaled when: Affected flag(s): Data (D7 to D0) Definition: Function: Signaled by: Signaled when: Affected flag(s): Description SDA0 (SDA1) falling edge when SCL is highNote 1 Indicates that serial communication starts and subsequent data is address data. Master CMDT is set. CMDD (is set.) SDA0 (SDA1) rising edge when SCL is highNote 1 Indicates end of serial transmission. Master RELT is set. RELD (is set) and CMDD (is cleared) Low level of SDA0 (SDA1) pin during one SCL clock cycle after serial reception Indicates completion of reception of 1 byte. Master or slave ACKT is set with ACKE = 1. ACKD (is set.) Low-level signal output to SCL Indicates state in which serial reception is not possible. Slave WAT1, WAT0 = 1x. None Synchronization clock for output of various signals Serial communication synchronization signal. Master See Note 2 below. CSIIF0. Also see Note 3 below. 7-bit data synchronized with SCL immediately after start condition signal Indicates address value for specification of slave on serial bus. Master See Note 2 below. CSIIF0. Also see Note 3 below. 1-bit data output in synchronization with SCL after address output Indicates whether data transmission or reception is to be performed. Master See Note 2 below. CSIIF0. Also see Note 3 below. 8-bit data synchronized with SCL, not immediately after start condition Contains data to be actually sent. Master or slave See Note 2 below. CSIIF0. Also see Note 3 below.
Notes 1. The level of the serial clock can be controlled with bit 3 (CLC) of interrupt timing specify register (SINT). 2. Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start directive). In the wait state, the serial transfer operation will be started after the wait state is released. 3. If the 8-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 8th clock cycle of SCL. If the 9-clock wait is selected when WUP = 0, CSIIF0 is set at the rising edge of the 9th clock cycle of SCL. CSIIF0 is set if an address is received and that address matches the value of the slave address register (SVA) when WUP = 1, or if the stop condition is detected.
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(5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output alternate-function pin. <1> Master ..... N-ch open-drain output <2> Slave ....... Schmitt input (b) SDA0 (SDA1) Serial data I/O alternate-function pin. Uses N-ch open-drain output and Schmitt-input buffers for both master and slave devices. Note that pull-up resistors are required to be connected to both the serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (SCL) and the serial data bus pin (SDA0 or SDA1) on the I2C bus. Figure 17-21. Pin Configuration
VDD0 Master device SCL Clock output VSS0 (Clock input) SDA0 (SDA1) Data output VSS0 Data input SDA0 (SDA1) VSS0 Data input Data output VDD0 VSS0 Clock input SCL (Clock output) Slave devices
Caution To receive data, the N-ch open-drain output must made to go into a high-impedance state. Therefore, set bit 7 (BSYE) of the serial bus interface control register (SBIC) to 1 in advance, and write FFH to serial I/O shift register 0 (SIO0). When the wakeup function is used (by setting bit 5 (WUP) of serial operating mode register 0 (CSIM0)), however, do not write FFH to SIO0 before reception. Even if FFH is not written to SIO0, the N-ch open-drain output always goes into a high-impedance state. (6) Address match detection method In the I2C mode, the master can select a specific slave device by sending slave address data. A match of the addresses can be automatically detected by hardware. CSIIF0 is set if the slave address transmitted by the master matches the value set to the slave address register (SVA) when a slave device address has a slave register (SVA), and the wakeup function specification bit (WUP) = 1 (CSIIF0 is also set when the stop condition is detected). When using the wakeup function, set SIC to 1. Caution Slave selection/non-selection is detected by matching of the data (address) received after the start condition. For this match detection, the match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
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(7) Error detection In the I2C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device. (a) Comparison of SIO0 data before and after transmission In this case, a transmission error is judged to have occurred if the two data values are different. (b) Using the slave address register (SVA) Transmit data is set in SIO0 and SVA before transmission is performed. After transmission, the COI bit (match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1" indicates normal transmission, and "0" indicates a transmission error.
(8) Communication operation In the I2C bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. After the slave address data, the master sends the R/W bit which indicates the data transfer direction, and starts serial communication with the selected slave device. Data communication timing charts are shown in Figures 17-22 and 17-23. In the transmitting device, serial I/O shift register 0 (SIO0) shifts transmission data to the SO latch in synchronization with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSBfirst basis from the SDA0 or SDA1 pin to the receiving device. In the receiving device, the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchronization with the rising edge of SCL.
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Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start condition to address
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 H H L L L L H H L L L L SIO0 FFH 12345 6 789 12 34 5 L L L H L L L L SIO0 Address SIO0 Data
A6 A5 A4 A3 A2 A1 A0 W ACK
D7 D6 D5 D4 D3
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Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 L H H L L L L H H L L L L SIO0 FFH SIO0 FFH 12345 D7 6 789 12 34 5 H L L L L L L L L L SIO0 Address SIO0 Data
D6 D5 D4 D3 D2 D1 D0 ACK
D7 D6 D5 D4 D3
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Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop condition
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 L L L H H H L SIO0 FFH SIO0 FFH 12345 D7 6 789 1 23 4 L L H L L L L SIO0 Data SIO0 Address
D6 D5 D4 D3 D2 D1 D0 ACK
A6 A5 A4 A3
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Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (1/3) (a) Start condition to address
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 L L L L H H L L L L SIO0 Data 12345 6 78 9 12 D7 34 5 L L L H L L SIO0 Address SIO0 FFH
A6 A5 A4 A3 A2 A1 A0 R ACK
D6 D5 D4 D3
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Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (2/3) (b) Data
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 L L L L L L L H H L L L L SIO0 Data SIO0 Data 12345 D7 6 78 9 12 D7 34 5 H L H H L L L L L L SIO0 FFH SIO0 FFH
D6 D5 D4 D3 D2 D1 D0 ACK
D6 D5 D4 D3
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Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) (3/3) (c) Stop condition
Master device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Transfer line SCL SDA0 Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 H H L L L L L L SIO0 Data 12345 D7 6 78 9 1 23 4 L L H L L SIO0 FFH SIO0 Address
D6 D5 D4 D3 D2 D1 D0 NAK
A6 A5 A4 A3
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(9) Transfer start A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied. * The serial interface channel 0 operation control bit (CSIE0) = 1. * After an 8-bit serial transfer, the internal serial clock is stopped or SCL is low. Cautions 1. Be sure to set CSIE0 to 1 before writing data in SIO0. Setting CSIE0 to 1 after writing data in SIO0 does not initiate transfer operation. 2. Because the N-ch open-drain output must made to go into a high-impedance state during data reception, set bit 7 (BSYE) of the serial bus interface control register (SBIC) to 1 before writing FFH to SIO0. Do not write FFH to SIO0 before reception when the wakeup function is used (by setting bit 5 (WUP) of serial operating mode register 0 (CSIM0)). Even if FFH is not written to SIO0, the N-ch open-drain output always goes into a high-impedance state. 3. If data is written to SIO0 while the slave is in the wait state, that data is held. The transfer is started when SCL is output after the wait state is cleared. When an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (CSIIF0) is set. 17.4.5 Cautions on use of I2C bus mode (1) Start condition output (master) The SCL pin normally outputs a low-level signal when no serial clock is output. It is necessary to change the SCL pin to high in order to output a start condition signal. Set CLC to 1 in the interrupt timing specification register (SINT) to drive the SCL pin high. After setting CLC, clear CLC to 0 and return the SCL pin to low. If CLC remains 1, no serial clock is output. If it is the master device which outputs the start condition and stop condition signals, confirm that CLD is set to 1 after setting CLC to 1; a slave device may have set SCL to low (wait state). Figure 17-24. Start Condition Output
SCL
SDA0 (SDA1)
CLC
CMDT
CLD
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(2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specification register (SINT)) setting or execution of a serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure 17-25, data should be transmitted by manipulating the P27 output latch through the program. At this time, control the low-level width ("a" in Figure 17-25) of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction. In addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the WREL flag of SINT and release the wait. For this timing, see Figure 17-23. Figure 17-25. Slave Wait Release (Transmission)
Master device operation Writing FFH to SIO0 Setting Setting ACKD CSIIF0
Software operation
Hardware operation
Serial reception
Transfer line
SCL
9
a1
2
3
SDA0 (SDA1)
A0
R
ACK
D7
D6
D5
Slave device operation
Software operation
P27 Write Output data latch 0 to SIO0
P27 Output latch 1
Hardware operation
ACK Setting output CSIIF0
Wait release
Serial transmission
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(3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specification register (SINT)) is set or when an instruction that writes data to serial I/O shift register 0 (SIO0) is executed. When the slave receives data, the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high-impedance state after an instruction that writes data to SIO has been executed. This is because SIO0 does not start operating if the SCL line is in the high-impedance state while the instruction that writes data to SIO0 is being executed (until the next instruction is executed). Therefore, receive the data by manipulating the output latch of P27 by program, as shown in Figure 17-26. For this timing, see Figure 17-22. Figure 17-26. Slave Wait Release (Reception)
Master device operation Writing data to SIO0
Software operation
Hardware operation
Setting Setting ACKD CSIIF0
Serial transmission
Transfer line
SCL
9
1
2
3
SDA0 (SDA1)
A0
W
ACK
D7
D6
D5
Slave device operation P27 Write Output FFH latch 0 to SIO0 P27 Output latch 1
Software operation
Hardware operation
ACK Setting output CSIIF0
Wait release
Serial reception
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(4) Reception completion of slave In the reception completion processing of the slave, check bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of serial operation mode register 0 (CSIM0) (when CMDD = 1). This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore the wakeup condition cannot be used when the slave receives an undefined number of data from the master.
17.4.6 Restrictions in I2C bus mode 1 The following restrictions are applied to the PD780058Y Subseries. * Restrictions when used as slave device in I2C bus mode Target device:
PD780053Y, 780054Y, 780055Y, 780056Y, 780058BY, 78F0058Y, IE-780308-R-EM,
IE-780308-NS-EM1
Description:
If the wakeup function is executed (by setting bit 5 of serial operating mode register 0 (CSIM0) to 1) in the serial transfer statusNote, the PD780058Y Subseries checks the address of the data between the other slaves and the master. If that data happens to match the slave address of the PD780058Y Subseries, the PD780058Y Subseries takes part in communication, destroying the communication data. Note The serial transfer status is the status from when data is written to serial I/O shift register 0 (SIO0) until the interrupt request flag (CSIIF0) is set to 1 by completion of the serial transfer.
Preventive measure: The above phenomenon can be avoided by modifying the program. Before executing the wakeup function, execute the following program that clears the serial transfer status. When executing the wakeup function, do not execute an instruction that writes data to SIO0. Even if such an instruction is not executed, data can be received when the wakeup function is executed. This program releases the serial transfer status. To release the serial transfer status, serial interface channel 0 must be disabled once (by clearing the CSIE0 flag (bit 7 of the serial operating mode register (CSIM0) to 0). If serial interface channel 0 is disabled in the I2C bus mode, however, the SCL pin outputs a high level, and the SDA0 (SDA1) pin outputs a low level, affecting communication of the I2C bus. Therefore, this program makes the SCL and SDA0 (SDA1) pins go into a high-impedance state to prevent the I2C bus from being affected. In this example, the SDA0 (/P25) pin is used as a serial data input/output pin. When SDA1 (/P26) is used, take P2.5 and PM2.5 in the program example below as P2.6 and PM2.6. For the timing of each signal when this program is executed, see Figure 17-22.
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* Example of program releasing serial transfer status SET1 SET1 SET1 CLR1 SET1 SET1 CLR1 CLR1 CLR1 <1> <2> P2.5; PM2.5; PM2.7; CSIE0; CSIE0; RELT; PM2.7; P2.5; PM2.5; <1> <2> <3> <4> <5> <6> <7> <8> <9>
This instruction prevents the SDA0 pin from outputting a low level when the I2C bus mode is restored by instruction <5>. The output of the SDA0 pin goes into a high-impedance state. This instruction sets the P25 (/SDA0) pin in the input mode to protect the SDA0 line from adverse influence when the port mode is set by instruction <4>. The P25 pin is set in the input mode when instruction <2> is executed.
<3>
This instruction sets the P27 (/SCL) pin in the input mode to protect the SCL line from adverse influence when the port mode is set by instruction <4>. The P27 pin is set in the input mode when instruction <3> is executed.
<4> <5> <6> <7> <8> <9>
This instruction changes the mode from I2C bus mode to port mode. This instruction restores the I2C bus mode from the port mode. This instruction prevents the SDA0 pin from outputting a low level when instruction <8> is executed. This instruction sets the P27 pin in the output mode because the P27 pin must be in the output mode in the I2C bus mode. This instruction clears the output latch of the P25 pin to 0 because the output latch of the P25 pin must be cleared to 0 in the I2C bus mode. This instruction sets the P25 pin in the output mode because the P25 pin must be in the output mode in the I2C bus mode.
Remark
RELT: Bit 0 of serial bus interface control register (SBIC)
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17.4.7 Restrictions in I2C bus mode 2 When using the I2C bus mode under the following conditions, the STOP condition is detected and an interrupt occurs when CSIE0 is set to 1. To enable the operation (by setting CSIE0 to 1), therefore, perform the following processing. Condition: If a low level is used when CSIE0 is set to 1 when using the P26/SDA as the SDA line and P25/SDA0 as an input port
(1) When operation is enabled SET1 SET1 CLR1 CLR1 CSIMK0 CSIE0 CSIIF0 CSIMK0 ; Disables INTCSI0 interrupt. ; Enables IIC operation. ; Clears INTCSI0 interrupt request flag. ; Enables INTCSI0 interrupt.
Cautions 1. After that, RELD = 1 (stop condition is detected) until data that does not match the source station slave address (SVA) is received. 2. Even if a start condition is satisfied while RELD = 1 (stop condition is detected), the interrupt occurs if it is enabled and CMDD = 1 (start condition is detected).
(2) When using as slave device in I2C bus mode (if restrictions in 17.4.6 apply) Example of program releasing serial transfer status SET1 SET1 SET1 SET1 CLR1 SET1 CLR1 CLR1 SET1 CLR1 CLR1 CLR1 CSIMK0 P2.6 PM2.6 PM2.7 CSIE0 CSIE0 CSIIF0 CSIMK0 RELT PM2.7 P2.6 PM2.6 ; Stops IIC operation. ; Enables IIC operation. ; Clears INTCSI0 interrupt request flag. ; Enables INTCSI0 interrupt. ; Disables INTCSI0 interrupt.
Cautions 1. After that, RELD = 1 (stop condition is detected) until data that does not match the source station slave address (SVA) is received. 2. Even if a start condition is satisfied while RELD = 1 (stop condition is detected), the interrupt occurs if it is enabled and CMDD = 1 (start condition is detected).
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17.4.8 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of the serial clock can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled by bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC)). The SCK0/SCL/P27 pin output should be manipulated as described below. (1) In 3-wire serial I/O mode and 2-wire serial I/O mode The output level of the SCK0/SCL/P27 pin is manipulated by the P27 output latch. <1> Set serial operating mode register 0 (CSIM0) (SCK0 pin: Output mode, serial operation: Enabled). SCK0 = 1 while serial transfer is stopped. <2> Manipulate the contents of the P27 output latch by executing a bit manipulation instruction. Figure 17-27. SCK0/SCL/P27 Pin Configuration
Manipulated by bit manipulation instruction SCK0/SCL/P27 To internal logic P27 Output latch
SCK0 (1 while transfer is stopped) CSIE0 = 1 and CSIM01, CSIM00 are 1, 0 or 1, 1, respectively From serial clock controller
(2) In I2C bus mode The output level of the SCK0/SCL/P27 pin is manipulated by the CLC bit of the interrupt timing specification register (SINT). <1> Set serial operating mode register 0 (CSIM0) (SCL pin: Output mode, serial operation: Enabled). Set the P27 output latch to 1. SCL = 0 while serial transfer is stopped. <2> Manipulate the CLC bit of SINT by executing a bit manipulation instruction. Figure 17-28. SCK0/SCL/P27 Pin Configuration
Set 1 SCK0/SCL/P27 To internal logic P27 Output latch
SCL CSIE0 = 1 and CSIM01 and CSIM00 are 1, 0 or 1, 1, respectively
Note
From serial clock controller
Note
The level of the SCL signal is in accordance with the contents of the logic circuits shown in Figure 17-29.
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Figure 17-29. Logic Circuit of SCL Signal
CLC (manipulated by bit manipulation instruction) SCL Wait request signal Serial clock (low while transfer is stopped)
Remarks 1. This figure indicates the relationship of the signals and does not indicate the internal circuit. 2. CLC: Bit 3 of interrupt timing specification register (SINT)
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18.1 Functions of Serial Interface Channel 1
Serial interface channel 1 employs the following three modes. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. (2) 3-wire serial I/O mode (MSB-/LSB-first switchable) This mode is used for 8-bit data transfer using three lines: a serial clock (SCK1), serial output (SO1), and serial input (SI1). The 3-wire serial I/O mode enables simultaneous transmission/reception and so decreases the data transfer processing time. Since the start bit of 8-bit data to undergo serial transfer is switchable between the MSB and LSB, connection is enabled with either start bit device. The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K, and 17K Series. (3) 3-wire serial I/O mode with automatic transmit/receive function (MSB-/LSB-first switchable) This mode is equivalent to the 3-wire serial I/O mode with the addition of an automatic transmit/receive function. The automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. This function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and a device with built-in display controller/driver independently of the CPU, thus alleviating the software load. Caution When using the P23/STB/TxD1 and P24/BUSY/RxD1 pins in the asynchronous serial interface (UART) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid.
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18.2 Configuration of Serial Interface Channel 1
Serial interface channel 1 consists of the following hardware. Table 18-1. Configuration of Serial Interface Channel 1
Item Registers Configuration Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive interval specification register (ADTI) Port mode register 2 (PM2)Note
Control registers
Note
See Figures 6-5 and 6-7 Block Diagram of P20, P21, and P23 to P26 and Figures 6-6 and 6-8 Block Diagram of P22 and P27.
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Figure 18-1. Block Diagram of Serial Interface Channel 1
Internal bus Automatic data transmit/receive address pointer (ADTP)
Buffer RAM
Internal bus
ATE DIR SI1/ P20 PM21 SO1/ P21 PM23 STB/ TxD1/P23 BUSY/ RxD1/P24
P21 output latch
DIR Serial I/O shift register 1 (SIO1)
Automatic data transmit/receive interval specify register ADTI ADTI ADTI ADTI ADTI ADTI 7 4 3 2 1 0 Match
RE
Automatic data transmit/receive control register
ARLD ERCE ERR TRF STRB BUSY BUSY 1 0
Serial operating mode register 1 CSIE1 DIR ATE CSIM CSIM 11 10 TRF Selector
ADTI0 to ADTI4
5-bit counter
Handshake
ARLD Serial clock counter
Selector
INTCSI1
SIOI write
Clear R Q S
SCK1/ P22
Selector TO2
Selector
4
fXX/2 to fXX/28
PM22
P22 output latch
TCL TCL TCL TCL 37 36 35 34
Timer clock select register 3
Internal bus
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(1) Serial I/O shift register 1 (SIO1) This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/ reception (shift operations) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation. In transmission, data written to SIO1 is output to the serial output (SO1). In reception, data is read from the serial input (SI1) to SIO1. RESET input makes SIO1 undefined. Caution Do not write data to SIO1 while the automatic transmit/receive function is activated. (2) Automatic data transmit/receive address pointer (ADTP) This register stores the value of (the number of transmit data bytes - 1) while the automatic transmit/receive function is activated. As data is transferred/received, the pointer is automatically decremented. ADTP is set with an 8-bit memory manipulation instruction. The higher 3 bits must be cleared to 0. RESET input clears ADTP to 00H. Caution Do not write data to ADTP while the automatic transmit/receive function is activated. (3) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received.
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18.3 Control Registers of Serial Interface Channel 1
The following four registers are used to control serial interface channel 1. * * * * Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive interval specification register (ADTI)
(1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial interface channel 0.
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Figure 18-2. Format of Timer Clock Select Register 3
Symbol
7
6
5
4
3
2
1
0
Address FF43H
After reset 88H
R/W R/W
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL37 TCL36 TCL35 TCL34
Serial interface channel 1 serial clock selection MCS = 1 MCS = 0 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz)
0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28
Setting prohibited fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
Other than above
Setting prohibited
Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS: Bit 0 of oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz
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(2) Serial operating mode register 1 (CSIM1) This register sets the serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1 to 00H. Figure 18-3. Format of Serial Operation Mode Register 1
Symbol <7> 6 <5> ATE 4 0 3 0 2 0 1 0 Address FF68H After reset 00H R/W R/W
CSIM1 CSIE1 DIR
CSIM11 CSIM10
CSIM11 CSIM10
Serial interface channel 1 clock selection External clock input to SCK1 pinNote 1 8-bit timer register 2 (TM2) output Clock specified by bits 4 to 7 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
ATE 0 1 3-wire serial I/O mode
Serial interface channel 1 operating mode selection
3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SI1 pin function SI1/P20 (input)
SO1 pin function SO1 (CMOS output)
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Shift register Serial clock counter 1 operation operation control Operation stop Operation enable Count operation Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O) SCK1 (input) SCK1 (CMOS output)
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
0
x
x
x x
x
x
x
x x 1
Note 3 Note 3
1
0 1
1
0
0
1 0
SI1Note 3 SO1 (CMOS output) (input)
Notes 1. If the external clock input has been selected with CSIM11 cleared to 0, clear bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as a port function. 3. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of ADTC to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTC to 00H. Figure 18-4. Format of Automatic Data Transmit/Receive Control Register
Symbol ADTC <7> RE <6> <5> <4> <3> <2> <1> <0> Address FF69H After reset 00H R/W R/WNote 1
ARLD ERCE ERR
TRF STRB BUSY1 BUSY0
R/W
BUSY1 BUSY0 0 1 1 x 0 1
Busy input control Not using busy input Busy input enabled (active high) Busy input enabled (active low)
R/W
STRB 0 1
Strobe output control Strobe output disabled Strobe output enabled
R
TRF 0
Status of automatic transmit/receive functionNote 2 Detection of termination of automatic transmission/ reception. (This bit is set to 0 upon suspension of automatic transmission/reception or when ARLD = 0.) During automatic transmission/reception (This bit is set to 1 when data is written to SIO1.)
1
R ERR 0 1 R/W ERCE Error check control of automatic transmit/receive function 0 1 R/W ARLD Operating mode selection of automatic transmit/receive function 0 1 R/W RE 0 1 Receive control of automatic transmit/receive function Receive disabled Receive enabled One-shot mode Repetitive one-shot mode Error check disabled Error check enabled (only when BUSY1 = 1) Error detection of automatic transmit/receive function No error (This bit is set to 0 when data is written to SIO1.) Error occurred
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt request flag). Cautions 1. When an external clock input is selected by clearing bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0. 2. When using the P23/STB/TxD1 and P24/BUSY/RxD1 pins in the asynchronous serial interface (UART) mode of serial interface channel 2, the busy control option and busy & strobe control option are invalid. Remark x: don't care
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(4) Automatic data transmit/receive interval specification register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTI to 00H. Figure 18-5. Format of Automatic Data Transmit/Receive Interval Specification Register (1/4)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1 No control of interval by ADTINote 1
Data transfer interval control
Control of interval by ADTI (ADTI0 to ADTI4)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 5.0 MHz operation) MinimumNote 2 MaximumNote 2 20.0 s + 1.5/fSCK 32.8 s + 1.5/fSCK 45.6 s + 1.5/fSCK 58.4 s + 1.5/fSCK 71.2 s + 1.5/fSCK 84.0 s + 1.5/fSCK 96.8 s + 1.5/fSCK 109.6 s + 1.5/fSCK 122.4 s + 1.5/fSCK 135.2 s + 1.5/fSCK 148.0 s + 1.5/fSCK 160.8 s + 1.5/fSCK 173.6 s + 1.5/fSCK 186.4 s + 1.5/fSCK 199.2s + 1.5/fSCK 212.0 s + 1.5/fSCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
18.4 s + 0.5/fSCK 31.2 s + 0.5/fSCK 44.0 s + 0.5/fSCK 56.8 s + 0.5/fSCK 69.6 s + 0.5/fSCK 82.4 s + 0.5/fSCK 95.2 s + 0.5/fSCK 108.0 s + 0.5/fSCK 120.8 s + 0.5/fSCK 133.6 s + 0.5/fSCK 146.4 s + 0.5/fSCK 159.2 s + 0.5/fSCK 172.0 s + 0.5/fSCK 184.8 s + 0.5/fSCK 197.6 s + 0.5/fSCK 210.4 s + 0.5/fSCK
Notes 1. The interval is dependent only on the CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Cautions 1. 2. 3. 26 fXX + 28 + 0.5 , Maximum = (n + 1) x fXX fSCK 26 fXX + 36 fXX + 1.5 fSCK
Do not write anything to ADTI while automatic transmission/reception is in progress (bit 3 (TRF) of the ADTC register = 1). Be sure to clear bits 5 and 6 to 0. When controlling the data transfer interval by means of automatic transmission/reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid.
Remarks 1. fXX: 2. fX:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
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Figure 18-5. Format of Automatic Data Transmit/Receive Interval Specification Register (2/4)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 5.0 MHz operation) MinimumNote MaximumNote 224.8 s + 1.5/fSCK 237.6 s + 1.5/fSCK 250.4 s + 1.5/fSCK 263.2 s + 1.5/fSCK 276.0 s + 1.5/fSCK 288.8 s + 1.5/fSCK 301.6 s + 1.5/fSCK 314.4 s + 1.5/fSCK 327.2 s + 1.5/fSCK 340.0 s + 1.5/fSCK 352.8 s + 1.5/fSCK 365.6 s + 1.5/fSCK 378.4 s + 1.5/fSCK 391.2 s + 1.5/fSCK 404.0 s + 1.5/fSCK 416.8 s + 1.5/fSCK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
223.2 s + 0.5/fSCK 236.0 s + 0.5/fSCK 248.8 s + 0.5/fSCK 261.6 s + 0.5/fSCK 274.4 s + 0.5/fSCK 287.2 s + 0.5/fSCK 300.0 s + 0.5/fSCK 312.8 s + 0.5/fSCK 325.6 s + 0.5/fSCK 338.4 s + 0.5/fSCK 351.2 s + 0.5/fSCK 364.0 s + 0.5/fSCK 376.8 s + 0.5/fSCK 389.6 s + 0.5/fSCK 402.4 s + 0.5/fSCK 415.2 s + 0.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 26 fXX 26 fXX + 28 fXX + 36 fXX + 0.5 fSCK + 1.5 fSCK
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: Main system clock frequency (fX or fX/2) 2. fX: Main system clock oscillation frequency 3. fSCK: Serial clock frequency
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Figure 18-5. Format of Automatic Data Transmit/Receive Interval Specification Register (3/4)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1 No control of interval by ADTI
Note 1
Data transfer interval control
Control of interval by ADTI (ADTI0 to ADTI4)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 2.5 MHz operation) MinimumNote 2 MaximumNote 2 40.0 s + 1.5/fSCK 65.6 s + 1.5/fSCK 91.2 s + 1.5/fSCK 116.8 s + 1.5/fSCK 142.4 s + 1.5/fSCK 168.0 s + 1.5/fSCK 193.6 s + 1.5/fSCK 219.2 s + 1.5/fSCK 244.8 s + 1.5/fSCK 270.4 s + 1.5/fSCK 296.0 s + 1.5/fSCK 321.6 s + 1.5/fSCK 347.2 s + 1.5/fSCK 372.8 s + 1.5/fSCK 398.4 s + 1.5/fSCK 424.0 s + 1.5/fSCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
36.8 s + 0.5/fSCK 62.4 s + 0.5/fSCK 88.0 s + 0.5/fSCK 113.6 s + 0.5/fSCK 139.2 s + 0.5/fSCK 164.8 s + 0.5/fSCK 190.4 s + 0.5/fSCK 216.0 s + 0.5/fSCK 241.6 s + 0.5/fSCK 267.2 s + 0.5/fSCK 292.8 s + 0.5/fSCK 318.4 s + 0.5/fSCK 344.0 s + 0.5/fSCK 369.6 s + 0.5/fSCK 395.2 s + 0.5/fSCK 420.8 s + 0.5/fSCK
Notes 1. The interval is dependent only on the CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 26 fXX 26 fXX + + 28 fXX 36 fXX + 0.5 fSCK + 1.5 fSCK
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: 2. fX: 3. fSCK: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency Serial clock frequency
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Figure 18-5. Format of Automatic Data Transmit/Receive Interval Specification Register (4/4)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 2.5 MHz operation) MinimumNote MaximumNote 449.6 s + 1.5/fSCK 475.2 s + 1.5/fSCK 500.8 s + 1.5/fSCK 526.4 s + 1.5/fSCK 552.0 s + 1.5/fSCK 577.6 s + 1.5/fSCK 603.2 s + 1.5/fSCK 628.8 s + 1.5/fSCK 654.4 s + 1.5/fSCK 680.0 s + 1.5/fSCK 705.6 s + 1.5/fSCK 731.2 s + 1.5/fSCK 756.8 s + 1.5/fSCK 782.4 s + 1.5/fSCK 808.0 s + 1.5/fSCK 833.6 s + 1.5/fSCK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
446.4 s + 0.5/fSCK 472.0 s + 0.5/fSCK 497.6 s + 0.5/fSCK 523.2 s + 0.5/fSCK 548.8 s + 0.5/fSCK 574.4 s + 0.5/fSCK 600.0 s + 0.5/fSCK 625.6 s + 0.5/fSCK 651.2 s + 0.5/fSCK 676.8 s + 0.5/fSCK 702.4 s + 0.5/fSCK 728.0 s + 0.5/fSCK 753.6 s + 0.5/fSCK 779.2 s + 0.5/fSCK 804.8 s + 0.5/fSCK 830.4 s + 0.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 26 fXX 26 fXX + + 28 + 0.5 fXX fSCK 36 + 1.5 fXX fSCK
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: Main system clock frequency (fX or fX/2) 2. fX: Main system clock oscillation frequency 3. fSCK: Serial clock frequency
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18.4 Operations of Serial Interface Channel 1
The following three operating modes are available for serial interface channel 1. * * * Operation stop mode 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial I/O shift register 1 (SIO1) does not carry out shift operations either, and thus it can be used as an ordinary 8-bit register. In the operation stop mode, the P20/SI1, P21/SO1, P22/SCK1, P23/STB/TxD1, and P24/BUSY/RxD1 pins can be used as ordinary I/O ports. (1) Register setting The operation stop mode is set by serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1 to 00H.
Symbol <7> 6 <5> ATE 4 0 3 0 2 0 1 0 Address FF68H After reset 00H R/W R/W
CSIM1 CSIE1 DIR
CSIM11 CSIM10
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Shift register Serial clock counter 1 operation operation control Operation stop Operation enable Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O) SCK1 (input) SCK1 (CMOS output)
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
0
x
x
x x
x
x
x
x x 1
Note 2 Note 2
1
0 1
1
0
0
1 0
Count operation
SI1Note 2 SO1 (CMOS output) (input)
Notes 1. Can be used freely as a port function. 2. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of the automatic data transmit/receive control register (ADTC) to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is useful for connection of peripheral I/O units and display controllers which incorporate a conventional clocked serial interface such as the 75X/XL, 78K and 17K Series. Communication is carried out using the three lines of the serial clock (SCK1), serial output (SO1) and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set by serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1 to 00H.
Symbol <7> 6 <5> ATE 4 0 3 0 2 0 1 0 Address FF68H After reset 00H R/W R/W
CSIM1 CSIE1 DIR
CSIM11 CSIM10
CSIM11 CSIM10
Serial interface channel 1 clock selection External clock input to SCK1 pinNote 8-bit timer register 2 (TM2) output Clock specified by bits 4 to 7 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
ATE 0 1 3-wire serial I/O mode
Serial interface channel 1 operating mode selection
3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SO1 pin function SI1/P20 (Input)
SO1 pin function SO1 (CMOS output)
Note
If the external clock input has been selected by setting CSIM11 to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0.
Remark
x: don't care
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CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Shift register 1 Serial clock counter operation operation control Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O) SCK1 (input) SCK1 (CMOS output)
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
0
x
x
x x
x
x
x
x
Operation stop Operation enable
Note 2 Note 2
1
0 1
1
0
0
1 0
x 1
Count operation
SI1Note 2 SO1 (CMOS output) (input)
Notes 1. Can be used freely as a port function. 2. Can be used as P20 (CMOS input/output) when only transmission is performed (clear bit 7 (RE) of ADTC to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operations of serial I/O shift register 1 (SIO1) are carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin. The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1. Upon termination of 8-bit transfer, the SIO1 operation stops automatically and the interrupt request flag (CSIIF1) is set. Figure 18-6. 3-Wire Serial I/O Mode Timing
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF1 End of transfer Transfer start at the falling edge of SCK1 SIO1 write
Caution The SO1 pin becomes low level by writing SIO1.
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(3) MSB/LSB switching as the start bit In 3-wire serial I/O mode, it is possible to select transfer to start from the MSB or LSB. Figure 18-7 shows the configuration of serial I/O shift register 1 (SIO1) and the internal bus. As shown in the figure, the MSB/LSB can be read or written in reverse form. MSB/LSB switching as the start bit can be specified by bit 6 (DIR) of serial operating mode register 1 (CSIM1). Figure 18-7. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SO1 latch SI1 Shift register 1 (SIO1) D Q
SO1
SCK1
Start bit switching is realized by switching the bit order for data write to SIO1. The SIO1 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 1 (SIO1) when the following two conditions are satisfied. * * Serial interface channel 1 operation control bit (CSIE1) = 1 Internal serial clock is stopped or SCK1 is a high level after 8-bit serial transfer.
Caution If CSIE1 is set to 1 after data write to SIO1, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF1) is set.
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18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32 bytes of data without the use of software. Once transfer is started, the set number of bytes of the data prestored in the RAM can be transmitted, and the set number of bytes of data can be received and stored in the RAM. Handshake signals (STB and BUSY) are supported by hardware to transmit/receive data continuously. An OSD (On Screen Display) LSI and peripheral LSI including an LCD controller/driver can thus be connected without difficulty. (1) Register setting The 3-wire serial I/O mode with automatic transmit/receive function is set by serial operating mode register 1 (CSIM1), the automatic data transmit/receive control register (ADTC) and the automatic data transmit/ receive interval specification register (ADTI). (a) Serial operating mode register 1 (CSIM1) CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1 to 00H.
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Symbol
<7>
6
<5> ATE
4 0
3 0
2 0
1
0
Address
FF68H
After reset
00H
R/W R/W
CSIM1 CSIE1 DIR
CSIM11 CSIM10
CSIM11 CSIM10
Serial interface channel 1 clock selection External clock input to SCK1 pinNote 1 8-bit timer register 2 (TM2) output Clock specified by bits 4 to 7 of timer clock select register 3 (TCL3)
0 1 1
x 0 1
ATE 0 3-wire serial I/O mode
Serial interface channel 1 operating mode selection
1
3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SI1 pin function SI1/P20 (input)
SO1 pin function SO1 (CMOS output)
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Shift register 1 Serial clock counter operation operation control Operation stop Clear
SI1/P20 pin function
P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function
P22 (CMOS I/O)
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
0
1
x 0
x
1
x x
x 0
x 0
x 1 0
x x 1
Note 3 Note 3
Operation enable
Count operation
SI1Note 3 SO1 (CMOS (input) output)
SCK1 (input) SCK1 (CMOS output)
1
Notes 1. If the external clock input has been selected by clearing CSIM11 to 0, clear bit 1 (BUSY 1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as a port function. 3. Can be used as P20 (CMOS input/output) when only transmission is performed (clear bit 7 (RE) of ADTC to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTC to 00H.
Symbol ADTC <7> RE <6> <5> <4> <3> <2> <1> <0> Address FF69H After reset 00H R/W R/WNote 1
ARLD ERCE ERR
TRF STRB BUSY1 BUSY0
R/W
BUSY1 BUSY0 0 1 1 x 0 1
Busy input control Not using busy input Busy input enabled (active high) Busy input enabled (active low)
R/W
STRB 0 1
Strobe output control Strobe output disabled Strobe output enabled
R
TRF 0
Status of automatic transmit/receive functionNote 2 Detection of termination of automatic transmission/reception (This bit is set to 0 upon suspension of automatic transmission/reception or when ARLD = 0.) During automatic transmission/reception (This bit is set to 1 when data is written to SIO1.)
1
R
ERR 0 1
Error detection of automatic transmit/receive function No error (This bit is set to 0 when data is written to SIO1.) Error occurred
R/W
ERCE Error check control of automatic transmit/receive function 0 1 Error check disabled Error check enabled (only when BUSY1 = 1)
R/W
ARLD 0 1
Operating mode selection of automatic transmit/receive function One-shot mode Repetitive one-shot mode
R/W
RE 0 1
Receive control of automatic transmit/receive function Receive disabled Receive enabled
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt request flag). Caution When an external clock input is selected by clearing bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) to 0, clear STRB and BUSY1 of ADTC to 0, 0 (handshake control cannot be executed when an external clock is input). Remark x: don't care
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(c) Automatic data transmit/receive interval specification register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTI to 00H.
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1 No control of interval by ADTI
Note 1
Data transfer interval control
Control of interval by ADTI (ADTI0 to ADTI4)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 5.0 MHz operation) MinimumNote 2 MaximumNote 2 20.0 s + 1.5/fSCK 32.8 s + 1.5/fSCK 45.6 s + 1.5/fSCK 58.4 s + 1.5/fSCK 71.2 s + 1.5/fSCK 84.0 s + 1.5/fSCK 96.8 s + 1.5/fSCK 109.6 s + 1.5/fSCK 122.4 s + 1.5/fSCK 135.2 s + 1.5/fSCK 148.0 s + 1.5/fSCK 160.8 s + 1.5/fSCK 173.6 s + 1.5/fSCK 186.4 s + 1.5/fSCK 199.2 s + 1.5/fSCK 212.0 s + 1.5/fSCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
18.4 s + 0.5/fSCK 31.2 s + 0.5/fSCK 44.0 s + 0.5/fSCK 56.8 s + 0.5/fSCK 69.6 s + 0.5/fSCK 82.4 s + 0.5/fSCK 95.2 s + 0.5/fSCK 108.0 s + 0.5/fSCK 120.8 s + 0.5/fSCK 133.6 s + 0.5/fSCK 146.4 s + 0.5/fSCK 159.2 s + 0.5/fSCK 172.0 s + 0.5/fSCK 184.8 s + 0.5/fSCK 197.6 s + 0.5/fSCK 210.4 s + 0.5/fSCK
Notes 1. The interval is dependent only on the CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x 26 fXX + 28 fXX + 0.5 , Maximum = (n + 1) x fSCK 26 fXX + 36 fXX + 1.5 fSCK
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. fSCK: Serial clock frequency
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Symbol
7
6 0
5 0
4
3
2
1
0
Address FF6BH
After reset 00H
R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 5.0 MHz operation) MinimumNote MaximumNote 224.8 s + 1.5/fSCK 237.6 s + 1.5/fSCK 250.4 s + 1.5/fSCK 263.2 s + 1.5/fSCK 276.0 s + 1.5/fSCK 288.8 s + 1.5/fSCK 301.6 s + 1.5/fSCK 314.4 s + 1.5/fSCK 327.2 s + 1.5/fSCK 340.0 s + 1.5/fSCK 352.8 s + 1.5/fSCK 365.6 s + 1.5/fSCK 378.4 s + 1.5/fSCK 391.2 s + 1.5/fSCK 404.0 s + 1.5/fSCK 416.8 s + 1.5/fSCK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
223.2 s + 0.5/fSCK 236.0 s + 0.5/fSCK 248.8 s + 0.5/fSCK 261.6 s + 0.5/fSCK 274.4 s + 0.5/fSCK 287.2 s + 0.5/fSCK 300.0 s + 0.5/fSCK 312.8 s + 0.5/fSCK 325.6 s + 0.5/fSCK 338.4 s + 0.5/fSCK 351.2 s + 0.5/fSCK 364.0 s + 0.5/fSCK 376.8 s + 0.5/fSCK 389.6 s + 0.5/fSCK 402.4 s + 0.5/fSCK 415.2 s + 0.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 26 + fXX 26 + fXX 28 fXX + 0.5 fSCK
36 + 1.5 fSCK fXX
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. fSCK: Serial clock frequency
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Symbol
7
6 0
5 0
4
3
2
1
0
Address FF6BH
After reset 00H
R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1 No control of interval by ADT INote 1
Data transfer interval control
Control of interval by ADTI (ADTI0 to ADTI4)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 2.5 MHz operation) MinimumNote 2 MaximumNote 2 40.0 s + 1.5/fSCK 65.6 s + 1.5/fSCK 91.2 s + 1.5/fSCK 116.8 s + 1.5/fSCK 142.4 s + 1.5/fSCK 168.0 s + 1.5/fSCK 193.6 s + 1.5/fSCK 219.2 s + 1.5/fSCK 244.8 s + 1.5/fSCK 270.4 s + 1.5/fSCK 296.0 s + 1.5/fSCK 321.6 s + 1.5/fSCK 347.2 s + 1.5/fSCK 372.8 s + 1.5/fSCK 398.4 s + 1.5/fSCK 424.0 s + 1.5/fSCK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
36.8 s + 0.5/fSCK 62.4 s + 0.5/fSCK 88.0 s + 0.5/fSCK 113.6 s + 0.5/fSCK 139.2 s + 0.5/fSCK 164.8 s + 0.5/fSCK 190.4 s + 0.5/fSCK 216.0 s + 0.5/fSCK 241.6 s + 0.5/fSCK 267.2 s + 0.5/fSCK 292.8 s + 0.5/fSCK 318.4 s + 0.5/fSCK 344.0 s + 0.5/fSCK 369.6 s + 0.5/fSCK 395.2 s + 0.5/fSCK 420.8 s + 0.5/fSCK
Notes 1. The interval is dependent only on the CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x 26 fXX + 28 fXX + 36 fXX + 0.5 fSCK + 1.5 fSCK
6 Maximum = (n + 1) x 2 fXX
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. fSCK: Serial clock frequency
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Symbol
7
6 0
5 0
4
3
2
1
0
Address FF6BH
After reset 00H
R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fXX = 2.5 MHz operation) MinimumNote MaximumNote 449.6 s + 1.5/fSCK 475.2 s + 1.5/fSCK 500.8 s + 1.5/fSCK 526.4 s + 1.5/fSCK 552.0 s + 1.5/fSCK 577.6 s + 1.5/fSCK 603.2 s + 1.5/fSCK 628.8 s + 1.5/fSCK 654.4 s + 1.5/fSCK 680.0 s + 1.5/fSCK 705.6 s + 1.5/fSCK 731.2 s + 1.5/fSCK 756.8 s + 1.5/fSCK 782.4 s + 1.5/fSCK 808.0 s + 1.5/fSCK 833.6 s + 1.5/fSCK
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
446.4 s + 0.5/fSCK 472.0 s + 0.5/fSCK 497.6 s + 0.5/fSCK 523.2 s + 0.5/fSCK 548.8 s + 0.5/fSCK 574.4 s + 0.5/fSCK 600.0 s + 0.5/fSCK 625.6 s + 0.5/fSCK 651.2 s + 0.5/fSCK 676.8 s + 0.5/fSCK 702.4 s + 0.5/fSCK 728.0 s + 0.5/fSCK 753.6 s + 0.5/fSCK 779.2 s + 0.5/fSCK 804.8 s + 0.5/fSCK 830.4 s + 0.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if a minimum which is calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 26 fXX 26 fXX + 28 fXX + 36 fXX + 0.5 fSCK + 1.5 fSCK
Cautions 1. Do not write to ADTI during operation of the automatic data transmit/receive function. 2. Be sure to clear bits 5 and 6 to 0. 3. When controlling the data transfer interval by means of automatic transmission/ reception using ADTI, busy control (see 18.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fXX: 2. fX: Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. fSCK: Serial clock frequency
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(2) Automatic transmit/receive data setting (a) Transmit data setting <1> <2> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in order from higher address to lower address. Set the value obtained by subtracting 1 from the number of transmit data bytes to the automatic data transmit/receive address pointer (ADTP). (b) Automatic transmit/receive mode setting <1> <2> <3> <4> Set CSIE1 and ATE of serial operating mode register 1 (CSIM1) to 1. Set RE of the automatic data transmit/receive control register (ADTC) to 1. Set a data transmit/receive interval in the automatic data transmit/receive interval specification register (ADTI). Write any value to serial I/O shift register 1 (SIO1) (transfer start trigger).
Caution Writing any value to SIO1 orders the start of the automatic transmit/receive operation; the written value has no meaning. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data specified by ADTP is transferred to SIO1, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address specified by ADTP. * ADTP is decremented and the next data transmission/reception is carried out. Data transmission/ reception continues until the ADTP decremental output becomes 00H and the data at address FAC0H is output (end of automatic transmission/reception). * When automatic transmission/reception is terminated, TRF is cleared to 0.
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(3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. When the final byte has been sent, an interrupt request flag (CSIIF1) is set. However, judge the termination of auto transmit and receive not by CSIIF1, but by bit 3 (TRF) of the automatic data transmit/ receive control register (ADTC). If busy control and strobe control are not executed, the P23/STB/TxD1 and P24/BUSY/RxD1 pins can be used as normal I/O ports. Figure 18-8 shows the basic transmission/reception mode operation timing, and Figure 18-9 shows the operation flowchart. Figure 18-10 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received. Figure 18-8. Basic Transmission/Reception Mode Operation Timing
Interval SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1 TRF
Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer RAM after 1-byte transmission/ reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the maximum interval is dependent upon the CPU processing and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic data transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of automatic data transmit/receive control register (ADTC)
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Figure 18-9. Basic Transmission/Reception Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (Start trigger)
Write transmit data from internal buffer RAM to SIO1
Transmission/reception operation
Decrement pointer value
Hardware execution Write receive data from SIO1 to internal buffer RAM
Pointer value = 0
No
Yes
TRF = 0
No Software execution
Yes End
ADTP: Automatic data transmit/receive address pointer ADTI: SIO1: TRF: Automatic data transmit/receive interval specification register Serial I/O shift register 1 Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, the internal buffer RAM operates as follows. (i) Before transmission/reception (see Figure 18-10 (a)) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1. When transmission of the first byte is completed, receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIO1. (ii) 4th byte transmission/reception point (see Figure 18-10 (b)) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIO1. When transmission of the fourth byte is completed, receive data 4 (R4) is transferred from SIO1 to the internal buffer RAM, and ADTP is decremented. (iii) Completion of transmission/reception (see Figure 18-10 (c)) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1 to the internal buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation). Figure 18-10. Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (1/2) (a) Before transmission/reception
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3)
Receive data 1 (R1)
SIO1
5 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) 0 -1
ADTP
CSIIF1
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Figure 18-10.
Internal Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception
FADFH
FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3)
Receive data 4 (R4)
SIO1
2 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) 0 -1
ADTP
CSIIF1
(c) Completion of transmission/reception
FADFH
FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) 0 Receive data 4 (R4) Receive data 5 (R5)
SIO1
ADTP
FAC0H
Receive data 6 (R6)
1
CSIIF1
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(b) Basic transmission mode In this mode, 8-bit unit data is transmitted the specified number of times. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. When the final byte has been sent, an interrupt request flag (CSIIF1) is set. However, judge the termination of automatic transmit and receive not by CSIIF1, but by bit 3 (TRF) of the automatic data transmit/receive control register (ADTC). If a receive operation, busy control and strobe control are not executed, the P20/SI1, P23/STB/TxD1 and P24/BUSY/RxD1 pins can be used as normal I/O ports. Figure 18-11 shows the basic transmission mode operation timing, and Figure 18-12 shows the operation flowchart. Figure 18-13 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received. Figure 18-11. Basic Transmission Mode Operation Timing
Interval SCK1 SO1 CSIIF1 TRF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Cautions 1. Because, in the basic transmission mode, the automatic transmit/receive function reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon the CPU processing and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic data transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of automatic data transmit/receive control register (ADTC)
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Figure 18-12. Basic Transmission Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (Start trigger)
Write transmit data from internal buffer RAM to SIO1
Decrement pointer value
Transmit operation Hardware execution
Pointer value = 0
No
Yes
TRF = 0
No Software execution
Yes End
ADTP: Automatic data transmit/receive address pointer ADTI: SIO1: TRF: Automatic data transmit/receive interval specification register Serial I/O shift register 1 Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, the internal buffer RAM operates as follows. (i) Before transmission (see Figure 18-13 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1. When transmission of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIO1. (ii) 4th byte transmission point (see Figure 18-13 (b).) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the internal buffer RAM to SIO1. When transmission of the fourth byte is completed, ADTP is decremented. (iii) Completion of transmission (see Figure 18-13 (c).) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is set (INTCSI1 generation). Figure 18-13. Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (1/2) (a) Before transmission
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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Figure 18-13.
Internal Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 2 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) Completion of transmission
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
1
CSIIF1
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(c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing any data to serial I/O shift register 1 (SIO1) when bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. Unlike the basic transmission mode, after the final byte (data at address FAC0H) has been transmitted, the interrupt request flag (CSIIF1) is not set, the value at the time when transmission was started is set in the automatic data transmit/receive address pointer (ADTP) again, and the internal buffer RAM contents are transmitted again. When a reception operation, busy control and strobe control are not performed, the P20/SI1, P23/STB/ TxD1 and P24/BUSY/RxD1 pins can be used as normal I/O ports. The repeat transmission mode operation timing is shown in Figure 18-14, and the operation flowchart in Figure 18-15. Figure 18-16 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode. Figure 18-14. Repeat Transmission Mode Operation Timing
Interval SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Interval
Caution Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, an interval is inserted in the period up to the next transmission. As buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon the CPU operation and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic data transmit/receive interval).
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Figure 18-15. Repeat Transmission Mode Flowchart
Start
Write transmit data in internal buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (start trigger)
Write transmit data from internal buffer RAM to SIO1
Decrement pointer value
Transmit operation
Hardware execution Pointer value = 0 No
Yes
Reset ADTP
ADTP: Automatic data transmit/receive address pointer ADTI: SIO1: Automatic data transmit/receive interval specification register Serial I/O shift register 1
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In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, the internal buffer RAM operates as follows. (i) Before transmission (see Figure 18-16 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1. When transmission of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIO1. (ii) Upon completion of transmission of 6 bytes (see Figure 18-16 (b).) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is not set. The internal pointer value is reset in ADTP. (iii) 7th byte transmission point (see Figure 18-16 (c).) Transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1 again. When transmission of the first byte is completed, ADTP is decremented. Then transmit data 2 (T2) is transferred from the internal buffer RAM to SIO1. Figure 18-16. Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (1/2) (a) Before transmission
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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Figure 18-16.
Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmit Mode) (2/2)
(b) Upon completion of transmission of 6 bytes
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) 7th byte transmission point
FADFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) -1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
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(d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by clearing bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is cleared to 0. It is suspended upon completion of 8-bit data transfer. When suspended, bit 3 (TRF) of the automatic data transmit/receive control register (ADTC) is cleared to 0 after transfer of the 8th bit, and all the port pins used as serial interface alternate-function pins (P20/ SI1, P21/SO1, P22/SCK1, P23/STB/TxD1 and P24/BUSY/RxD1) are set to the port mode. To restart automatic transmission/reception, set CSIE1 to 1 and write the desired value to serial I/O shift register 1 (SIO1). The remaining data can be transmitted in this way. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, transfer is suspended and the HALT mode is set, even if 8-bit data transfer is in progress. When the HALT mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TRF = 1. Figure 18-17. Automatic Transmission/Reception Suspension and Restart
CSIE1 = 0 (suspended command) Suspend Restart command CSIE1 = 1, write to SIO1
SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIE1: Bit 7 of serial operating mode register 1 (CSIM1)
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(4) Synchronization control Busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active. When using this busy control option, the following conditions must be satisfied. * Bit 5 (ATE) of serial operating mode register 1 (CSIM1) is set to 1. * Bit 1 (BUSY1) of the automatic data transmit/receive control register (ADTC) is set to 1. Figure 18-18 shows the system configuration of the master device and a slave device when the busy control option is used. Figure 18-18. System Configuration When Busy Control Option Is Used
Master device ( PD780058, 780058Y Subseries) SCK1 SO1 SI1 BUSY
Slave device SCK1 SI1 SO1
The master device inputs the busy signal output by the slave device to the BUSY/P24 pin. The master device samples the input busy signal in synchronization with the falling edge of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception by the master is not kept waiting. If the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission/reception of the 8-bit data, the busy input becomes valid. After that, the master transmission/reception is kept waiting while the busy signal is active. The active level of the busy signal is set by bit 0 (BUSY0) of ADTC. BUSY0 = 0: Active high BUSY0 = 1: Active low When using the busy control option, select the internal clock as the serial clock. Control with the busy signal cannot be implemented with an external clock. Figure 18-19 shows the operation timing when the busy control option is used. Caution Busy control cannot be used simultaneously with the interval time control function of the automatic data transmit/receive interval specification register (ADTI). If used, busy control is invalid.
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Figure 18-19. Operation Timing When Busy Control Option Is Used (When BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY Wait CSIIF1 Clears busy input Busy input is valid TRF
Caution If TRF is cleared, the SO1 pin goes low. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
When the busy signal becomes inactive, waiting is released. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next clock. Because the busy signal is asynchronous to the serial clock, it takes up to 1 clock until the busy signal is sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy signal was sampled. To accurately release waiting, the slave must keep the busy signal inactive at least for the duration of 1.5 clocks. Figure 18-20 shows the timing of the busy signal and wait release. This figure shows an example where the busy signal is active as soon as transmission/reception has been started.
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Figure 18-20. Busy Signal and Wait Release (When BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY (Active high)
1.5 clocks (min.) If made inactive immediately after sampled Wait Busy input released Busy input valid
(b) Busy & strobe control option Strobe control is a function to synchronize data transmission/reception between the master and slave devices. The master device outputs the strobe signal from the STB/P23 pin when 8-bit transmission/ reception has been completed. By this signal, the slave device can determine the timing of the end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift. To use the strobe control option, the following conditions must be satisfied. * Bit 5 (ATE) of serial operating mode register 1 (CSIM1) is set to 1. * Bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) is set to 1. Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this case, the strobe signal is output from the STB/P23 pin, the BUSY/P24 pin is sampled, and transmission/reception can be kept waiting while the busy signal is input. When the strobe control option is not used, the P23/STB pin can be used as a normal I/O port pin. Figure 18-21 shows the operation timing when the busy & strobe control options are used. When the strobe control option is used, the interrupt request flag (CSIIF1) that is set on completion of transmission/reception is set after the strobe signal is output.
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Figure 18-21. Operation Timing When Busy & Strobe Control Options Are Used (When BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STB
BUSY
CSIIF1 Busy input released Busy input valid TRF
Caution When TRF is cleared, the SO1 pin goes low. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
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(c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte. In this case, the master can detect the bit shift by checking the busy signal during transmission by using the busy control option. A bit shift is detected by using the busy signal as follows. The slave outputs the busy signal after the rising of the eighth serial clock during data transmission/ reception (to not keep transmission/reception waiting by the busy signal at this time, make the busy signal inactive within 2 clocks). The master samples the busy signal in synchronization with the falling edge of the leading side of the serial clock. If a bit shift does not occur, all the eight serial clocks that have been sampled are inactive. If the sampled serial clocks are active, it is assumed that a bit shift has occurred, and error processing is executed (by setting bit 4 (ERR) of the automatic data transmit/receive control register (ADTC) to 1). Figure 18-22 shows the operation timing of the bit shift detection function by the busy signal. Figure 18-22. Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSY0 = 1)
SCK1 (master) Bit shift due to noise SCK1 (slave) SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
BUSY
CSIIF1
CSIE1
ERR Busy not detected Error interrupt request generated Error detected
CSIIF1: Interrupt request flag CSIE1: Bit 7 of serial operating mode register 1 (CSIM1) ERR: Bit 4 of the automatic data transmit/receive control register (ADTC)
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(5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive operation. Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit/receive function with the internal clock, the interval depends on the value which is set in the automatic transmit/receive interval specification register (ADTI) and the CPU processing at the rising edge of the eighth serial clock. Whether it depends on the ADTI or not can be selected by setting bit 7 of ADTI (ADTI7). When it is cleared to 0, the interval depends only on the CPU processing. When it is set to 1, the interval depends on the contents of ADTI or the CPU processing, whichever is greater. When the automatic transmit/receive function is used with an external clock, it must be selected so that the interval may be longer than the value indicated by paragraph (b). Figure 18-23. Automatic Data Transmit/Receive Interval Time
Interval SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
CSIIF1: Interrupt request flag
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(a) When the automatic transmit/receive function is used with the internal clock If bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is set to 1, the internal clock operates. If the automatic transmit/receive function is operated with the internal clock, the interval timing according to CPU processing is as follows. When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is cleared to 0, the interval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of ADTI or the CPU processing, whichever is greater. See Figure 18-5 Automatic Data Transmit/Receive Interval Specification Register Format for the intervals set by ADTI. Table 18-2. Interval Timing According to CPU Processing (When Internal Clock Is Operating)
CPU Processing When using multiplication instruction When using division instruction External access 1 wait mode Other than above Interval Time Max. (2.5TSCK, 13TCPU) Max. (2.5TSCK, 20TCPU) Max. (2.5TSCK, 9TCPU) Max. (2.5TSCK, 7TCPU)
TSCK: fSCK: TCPU: fCPU: MAX. (a, b):
1/fSCK Serial clock frequency 1/fCPU CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) and bit 0 (MCS) of the oscillation mode select register (OSMS)) a or b, whichever is greater
Figure 18-24. Operation Timing with Automatic Data Transmit/Receive Function Performed Using Internal Clock
fX TCPU fCPU TSCK SCK1 SO1 SI1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Interval
fX:
Main system clock oscillation frequency
fCPU: CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)) TCPU: 1/fCPU TSCK: 1/fSCK fSCK: Serial clock frequency
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(b) When using automatic transmit/receive function with external clock An external clock is used when bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0. To use the automatic transmit/receive function with an external clock, the external clock must be input so that the interval time is as follows. Table 18-3. Interval Time According to CPU Processing (with External Clock)
CPU Processing When using multiplication instruction When using division instruction External access 1 wait mode Other than above Interval Time 13TCPU or more 20TCPU or more 9TCPU or more 7TCPU or more
TCPU: 1/fCPU fCPU: CPU clock (set by the bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) and bit 0 (MCS) of the oscillation mode select register (OSMS))
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19.1 Functions of Serial Interface Channel 2
Serial interface channel 2 has the following three modes. * Operation stop mode * Asynchronous serial interface (UART) mode (with time-division transfer function) * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption. (2) Asynchronous serial interface (UART) mode (with time-division transfer function) In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by dividing the clock input to the ASCK pin. The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator. Two sets of data I/O pins (RxD and TxD) are provided, and the pin to be used can be selected by software (time-division transfer function). However, only one set of pins can be used at one time. Cautions 1. If it is not necessary to change the data I/O pin, use of the RxD0/SI2/P70 and TxD0/SO2/ P71 pins is recommended. If only port 2 (RxD1/BUSY/P24 and TxD1/STB/P23) is used as data I/O pins, the function of port 7 is limited. 2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transmit/receive function of serial interface channel 1, the RxD1/ BUSY/P24 and TxD1/STB/P23 pins cannot be used as data I/O pins. (3) 3-wire serial I/O mode (MSB-first/LSB-first switchable) In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines (SI2, SO2). In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed. Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc.
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19.2 Configuration of Serial Interface Channel 2
Serial interface channel 2 consists of the following hardware. Table 19-1. Configuration of Serial Interface Channel 2
Item Registers Configuration Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Serial operating mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Serial interface pin select register (SIPS)
Control registers
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Figure 19-1. Block Diagram of Serial Interface Channel 2
Internal bus
Serial interface pin select register SIPS21 SIPS20 Receive buffer register (RXB/SIO2) PE FE
Asynchronous serial interface status register OVE Direction controller
Asynchronous serial interface mode register TXE RXE PS1 PS0 CL SL ISRM SCK
Direction controller RxD0/SI2/P70 RxD1/BUSY/P24
Transmit shift register (TXS/SIO2)
Selector
Receive shift register (RXS)
TxD0/SO2/P71 PM71 TxD1/STB/P23 PM23 PM72 ASCK/ SCK2/P72
Selector
Reception controller
INTSER INTSR/INTCSI2 ISRM
Transmission controller
SCK Output controller INTST
Note Baud rate generator
CSIE2 TXE RXE
fXX to f XX/210
SCK CSCK
4
4
CSIE2
CSIM CSCK 22
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Serial operating mode register 2
Baud rate generator control register Internal bus
Note
See Figure 19-2 for the baud rate generator configuration.
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Figure 19-2. Baud Rate Generator Block Diagram
CSIE2 TXE
Start bit sampling clock
Selector
Selector
5-bit counter
1/2
Selector
Transmit clock
ASCK/SCK2/P72 Selector
Match MDL0 to MDL3
fXX to f XX/210 TPS0 to TPS3 SCK CSCK
4
Decoder
4
Receive clock
Selector
1/2
Match
5-bit counter
4
RXE Start bit detection
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Baud rate generator control register
Internal bus
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(1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS is written with an 8-bit memory manipulation instruction. It cannot be read. RESET input sets TXS to FFH. Caution TXS must not be written during a transmit operation. TXS and the receive buffer register (RXB) are allocated to the same address, and when a read is performed, the value of RXB is read. (2) Receive shift register (RXS) This register is used to convert serial data input to the RxD0 (RxD1) pin into parallel data. When one byte of data is received, the receive data is transferred to the receive buffer register (RXB). RXS cannot be directly manipulated by a program. (3) Receive buffer register (RXB) This register holds receive data. Each time one byte of data is received, new receive data is transferred from the receive shift register (RXS). If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of RXB is always cleared to 0. RXB is read with an 8-bit memory manipulation instruction. It cannot be written to. RESET input sets RXB to FFH. Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write is performed, the value is written to TXS. (4) Transmission controller This circuit performs transmit operation control such as the addition of a start bit, parity bit, and stop bit to data written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial interface mode register (ASIM). (5) Reception controller This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with the error contents.
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19.3 Control Registers of Serial Interface Channel 2
Serial interface channel 2 is controlled by the following five registers. * Serial operating mode register 2 (CSIM2) * Asynchronous serial interface mode register (ASIM) * Asynchronous serial interface status register (ASIS) * Baud rate generator control register (BRGC) * Serial interface pin select register (SIPS) (1) Serial operating mode register 2 (CSIM2) This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode. CSIM2 is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input sets CSIM2 to 00H. Figure 19-3. Format of Serial Operating Mode Register 2
Symbol <7> 6 0 5 0 4 0 3 0 2 1 0
0
Address FF72H
After reset 00H
R/W R/W
CSIM2 CSIE2
CSIM CSCK 22
CSCK 0 1
Clock selection in 3-wire serial I/O mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output
CSIM22
First bit specification MSB LSB
0 1
CSIE2 0 1
Operation control in 3-wire serial I/O mode Operation stopped Operation enabled
Cautions 1. Be sure to clear bits 0 and 3 to 6 to 0. 2. When UART mode is selected, CSIM2 should be cleared to 00H.
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(2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. Figure 19-4. Format of Asynchronous Serial Interface Mode Register
Symbol ASIM <7> TXE <6> RXE 5 PS1 4 PS0 3 CL 2 SL 1 0 Address FF70H After reset 00H R/W R/W
ISRM SCK
SCK 0 1 ISRM 0 1
Clock selection in asynchronous serial interface mode Input clock from off-chip to ASCK pin Dedicated baud rate generator outputNote Control of reception completion interrupt request in case of error occurrence Reception completion interrupt request generated in case of error occurrence Reception completion interrupt request not generated in case of error occurrence Transmit data stop bit length specification 1 bit 2 bits Character length specification 7 bits 8 bits PS0 0 1 No parity 0 parity always added in transmission. No parity test in reception (parity error not generated). Odd parity Even parity Receive operation control Receive operation stopped Receive operation enabled Transmit operation control Transmit operation stopped Transmit operation enabled Parity bit specification
SL 0 1 CL 0 1 PS1 0 0
1 1 RXE 0 1 TXE 0 1
0 1
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an I/O port.
Cautions 1. When the 3-wire serial I/O mode is selected, ASIM should be cleared to 00H. 2. The serial transmit/receive operation must be stopped before changing the operating mode.
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Table 19-2. Operating Mode Settings of Serial Interface Channel 2 (1/2) (1) Operation stop mode
PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 Start Shift P70/SI2/ P71/SO2/ P23/STB/ P24/BUSY/ P72/SCK2 bit clock RxD0 pin TxD0 pin TxD1 pin RxD1 pin /ASCK pin TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 function function function function function 0 0 x 0 x x x x xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 xNote 1 -- Other than above -- P70 P71 P23/STB P24/BUSY P72 ASIM CSIM2 SIPS
Setting prohibited
(2) 3-wire serial I/O mode
PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 Start Shift P70/SI2/ P71/SO2/ P23/STB/ P24/BUSY/ P72/SCK2 bit clock RxD0 pin TxD0 pin TxD1 pin RxD1 pin /ASCK pin TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 function function function function function 0 0 0 1 0 0 x xx
Note 2 Note 2
ASIM
CSIM2
SIPS
x
0
1x
Note 1
x
Note 1
x
Note 1
x
Note 1
1
x 1 x 1
MSB External SI2 clock Internal clock
Note 2
SO2 (CMOS output)
P23/STB P24/BUSY SCK2 input
1
0
SCK2 output SO2 (CMOS output)
1
1
0
1
LSB External SI2 Note 2 clock Internal clock
SCK2 input
1
0
SCK2 output
Other than above
Setting prohibited
Notes 1. Can be used freely as a port function. 2. Can be used as P70 (CMOS I/O) when only transmission is performed. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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Table 19-2. Operating Mode Setting of Serial Interface Channel 2 (2/2) (3) Asynchronous serial interface mode
PM70 P70 PM71 P71 PM23 P23 PM24 P24 PM72 P72 Start Shift P70/SI2/ P71/SO2/ P23/STB/ P24/BUSY/ P72/SCK2 bit clock RxD0 pin TxD0 pin TxD1 pin RxD1 pin /ASCK pin TXE RXE SCK CSIE2 CSIM22 CSCK SIPS21 SIPS20 function function function function function 1 0 0 0 0 0 0 0x
Note 1 Note 1
ASIM
CSIM2
SIPS
x
0
1x
Note 1
x
Note 1
x
Note 1
x
Note 1
1
x
LSB External clock Internal clock External clock Internal clock External clock Internal clock External clock Internal clock External clock Internal clock External clock Internal clock
P70
TxD0 (CMOS output)
P23/STB P24/BUSY ASCK input
1 x x
Note 1
x 0 0 0 0 0 1 x
Note 1
Note 1
x
Note 1
P72
0
1
0
x
Note 1
x
Note 1
x
Note 1
x
Note 1
1
x
RxD0
P71
ASCK input
1 x
x 0 0 0 0 0 1 0
Note 1
x
Note 1
P72
1
1
0
1 xNote 1 xNote 1 xNote 1 xNote 1 1 x
Note 1
x
TxD0 (CMOS output)
ASCK input
1 0x
Note 1
x
Note 1
P72
1
0
0
0
0
0
1
x
Note 1
0
1
0 Note 2 x
Note 1
x
Note 1
1
x
P70
High output
TxD1
P24/BUSY ASCK input
1 xx
Note 1
x 0 0 0 0 1 1 x
Note 1
Note 1
x
Note 1
P72
0
1
0
x
Note 1
x
Note 1
1
x
1
x
P70 (Input)
P71
P23/STB
RxD1
ASCK input
1 x x
x 0 0 0 1 1 1 0 1 0 Note 2 1
Note 1
x
Note 1
P72
1
1
0
1
x
P70 (Input)
High output
TxD1
RxD1
ASCK input
1
x Other than above
Note 1
x
Note 1
P72
Setting prohibited
Notes 1. Can be used freely as a port function. 2. The set value differs between when the actual device operates and when emulation is executed by the in-circuit emulator. For details, see 19.4.5 Restrictions in UART mode 2. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
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(3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error occurs in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of ASIS are undefined. RESET input clears ASIS to 00H. Figure 19-5. Format of Asynchronous Serial Interface Status Register
Symbol ASIS 7 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FF71H After reset 00H R/W R
OVE 0 1
Overrun Error Flag Overrun error did not occur Overrun error occurredNote 1 (When next receive operation is completed before data is read from receive buffer register)
FE 0 1
Framing error flag Framing error did not occur Framing error occurredNote 2 (When stop bit is not detected)
PE 0 1
Parity error flag Parity error did not occur Parity error occurred (when transmit data parity does not match)
Notes 1. The receive buffer register (RXB) must be read when an overrun error occurs. Overrun errors will continue to occur until RXB is read. 2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only single stop bit detection is performed during reception.
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(4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H. Figure 19-6. Format of Baud Rate Generator Control Register (1/2)
Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After reset 00H R/W R/W
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCKNote
Baud rate generator input clock selection 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
k
--
Note
Can only be used in 3-wire serial I/O mode.
Remarks 1. fSCK: 5-bit counter source clock 2. k: Value set in MDL0 to MDL3 (0 k 14)
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Figure 19-6. Format of Baud Rate Generator Control Register (2/2)
TPS3 TPS2 TPS1 TPS0 5-bit counter source clock selection MCS = 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29 fXX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 (4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 MCS = 0 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz) 11 1 2 3 4 5 6 7 8 9 10 n
Other than above
Setting prohibited
Caution When BRGC is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written during a communication operation. Remarks 1. fX: 2. fXX: 4. n: Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11)
3. MCS: Bit 0 of the oscillation mode select register (OSMS) 5. Values in parentheses apply to operation with fX = 5.0 MHz
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The baud rate transmit/receive clock generated is either a signal divided from the main system clock, or a signal divided from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock from main system clock The transmit/receive clock is generated by dividing the main system clock. The baud rate generated from the main system clock is obtained from the following expression. [Baud rate] = fXX 2n x (k + 16) [Hz]
where,
fX: fXX: n: k:
Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11) Value set in MDL0 to MDL3 (0 k 14)
Table 19-3. Relationship Between Main System Clock and Baud Rate
Baud Rate (bps) fX = 5.0 MHz MCS = 1 MCS = 0 MCS = 1 fX = 4.19 MHz MCS = 0 Error (%) BRGC Set Value Error (%) 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 1.14 EBH E3H DBH CBH BBH ABH 9BH 8BH 7BH 6BH 61H 5BH -- 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 --
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value 75 110 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 06H 00H E0H D0H C0H B0H A0H 90H 80H 74H 70H 60H - 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 00H E6H E0H D0H C0H B0H A0H 90H 80H 70H 64H 60H 50H 1.73 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 0BH 03H EBH DBH CBH BBH ABH 9BH 8BH 7BH 71H 6BH 5BH
Remark
MCS: Bit 0 of the oscillation mode select register (OSMS)
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(b) Generation of baud rate transmit/receive clock from external clock input from ASCK pin The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained from the following expression. [Baud rate] = fASCK 2 x (k + 16) fASCK: k: [Hz]
Frequency of clock input to ASCK pin Value set in MDL0 to MDL3 (0 k 14)
Table 19-4. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Baud Rate (bps) 75 110 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK Pin Input Frequency 2.4 kHz 3.52 kHz 4.8 kHz 9.6 kHz 19.2 kHz 38.4 kHz 76.8 kHz 153.6 kHz 307.2 kHz 614.4 kHz 1,000.0 kHz 1,228.8 kHz
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(5) Serial interface pin select register (SIPS) This register selects the input/output pins when serial interface channel 2 is used in the asynchronous serial interface mode (with time-division transfer function). SIPS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SIPS to 00H. To select the input/output pins, the port mode register and the output latch of the port must be set. For details, see Table 19-2 Operating Mode Settings of Serial Interface Channel 2. Figure 19-7. Format of Serial Interface Pin Select Register
Symbol SIPS 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Address FF75H After reset 00H R/W R/W
SIPS21 SIPS20
SIPS21 SIPS20 0 0 1 1 0 1 0 1
Selection input/output pin of asynchronous serial interface Input pin: RxD0/SI2/P70 Output pin: TxD0/SO2/P71 Input pin: RxD1/BUSY/P24 Output pin: TxD0/SO2/P71 Input pin: RxD0/SI2/P70 Output pin: TxD1/STB/P23 Input pin: RxD1/BUSY/P24 Output pin: TxD1/STB/P23
Cautions 1. Select the input/output pins after stopping serial transmission/reception. 2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transmit/receive function of serial interface channel 1, the RxD1/ BUSY/P24 and TxD1/STB/P23 pins cannot be used as data I/O pins. 3. SIPS21 is valid only when the TXE flag is "1" and SIPS20 is valid only when the RXE flag is "1". 4. There are restrictions when SIPS21 = 1 (when the TxD1 pin is used as an output pin for UART transmission). For details, see 19.4.5 Restrictions in UART mode 2.
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19.4 Operation of Serial Interface Channel 2
The following three operating modes are available for serial interface channel 2. * Operation stop mode * Asynchronous serial interface (UART) mode (with time-division transfer function) * 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. In the operation stop mode, the P70/SI2/RxD0, P71/SO2/TxD0, and P72/SCK2/ASCK pins can be used as normal I/O ports and the P23/STB/TxD1, P24/BUSY/RxD1 pins can be used as normal I/O ports or as the strobe output and busy input for serial interface automatic transmit/receive. (1) Register setting Operation stop mode is set by serial operating mode register 2 (CSIM2) and the asynchronous serial interface mode register (ASIM). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM2 to 00H.
Symbol <7> 6 0 5 0 4 0 3 0 2 1 0 0 Address FF72H After reset 00H R/W R/W
CSIM2 CSIE2
CSIM CSCK 22
CSIE2 0 1
Operation control in 3-wire serial I/O mode Operation stopped Operation enabled
Caution Be sure to clear bits 0 and 3 to 6 to 0.
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(b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H.
Symbol ASIM <7> TXE <6> RXE 5 PS1 4 PS0 3 CL 2 SL 1 0 Address FF70H After reset 00H R/W R/W
ISRM SCK
RXE 0 1
Receive operation control Receive operation stopped Receive operation enabled
TXE 0 1
Transmit operation control Transmit operation stopped Transmit operation enabled
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19.4.2 Asynchronous serial interface (UART) mode (with time-division transfer function) In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by dividing the clock input to the ASCK pin. The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator. Two sets of data I/O pins (RxD and TxD) are provided, and the pin to be used can be selected by software (timedivision transfer function). However, only one set of pins can be used at one time. Cautions 1. If it is not necessary to change the data I/O pin, use of the RxD0/SI2/P70 and TxD0/SO2/P71 pins is recommended. If only port 2 (RxD1/BUSY/P24 and TxD1/STB/P23) is used as data I/O pins, the function of port 7 is limited. 2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transmit/receive function of serial interface channel 1, the RxD1/BUSY/ P24 and TxD1/STB/P23 pins cannot be used as data I/O pins. (1) Register setting UART mode (with time-division transfer function) is set by serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), the asynchronous serial interface status register (ASIS), the baud rate generator control register (BRGC), and the serial interface pin select register (SIPS). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM2 to 00H. When the UART mode is selected, CSIM2 should be cleared to 00H.
Symbol
<7>
6 0
5 0
4 0
3 0
2
1
0
0
Address FF72H
After reset 00H
R/W R/W
CSIM2 CSIE2
CSIM CSCK 22
CSCK 0 1
Clock selection in 3-wire serial I/O mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output
CSIM22
First bit specification MSB LSB
0 1
CSIE2 0 1
Operation control in 3-wire serial I/O mode Operation stopped Operation enabled
Caution Be sure to clear bits 0 and 3 to 6 to 0.
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(b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H.
Symbol ASIM <7> TXE <6> RXE 5 PS1 4 PS0 3 CL 2 SL 1 0 Address FF70H After reset 00H R/W R/W
ISRM SCK
SCK Clock selection in asynchronous serial interface mode 0 1 Input clock from off-chip to ASCK pin Dedicated baud rate generator outputNote
ISRM 0 1
Control of reception completion interrupt request in case of error occurrence Reception completion interrupt request generated in case of error occurrence Reception completion interrupt request not generated in case of error occurrence
SL 0 1 1 bit
Transmit data stop bit length specification
2 bits
CL 0 1 7 bits 8 bits
Character length specification
PS1 0 0
PS0 0 1 No parity
Parity bit specification
0 parity always added in transmission. No parity test in reception (parity error not generated). Odd parity Even parity
1 1
0 1
RXE 0 1
Receive operation control Receive operation stopped Receive operation enabled
TXE 0 1
Transmit operation control Transmit operation stopped Transmit operation enabled
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an I/O port.
Caution The serial transmit/receive operation must be stopped before changing the operating mode.
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(c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS to 00H.
Symbol ASIS 7 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FF71H After reset 00H R/W R
OVE 0 1
Overrun error flag Overrun error did not occur Overrun error occurredNote 1 (When next receive operation is completed before data from receive buffer register is read)
FE 0 1
Framing error flag Framing error did not occur Framing error occurredNote 2 (When stop bit is not detected)
PE 0 1
Parity error flag Parity error did not occur Parity error occurred (When transmit data parity does not match)
Notes 1. The receive buffer register (RXB) must be read when an overrun error occurs. Overrun errors will continue to occur until RXB is read. 2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only single stop bit detection is performed during reception.
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(d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H.
Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After reset 00H R/W R/W
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30
Baud rate generator input clock selection 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
k
(Cont'd) Remark fSCK: 5-bit counter source clock k: Value set in MDL0 to MDL3 (0 k 14)
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TPS3 TPS2
TPS1 TPS0
5-Bit counter source clock selection MCS = 1 MCS = 0 fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz)
n
0 0 0 0 1 1 1 1 1 1 1
0 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0
fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29
fX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29
(4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz)
11 1 2 3 4 5 6 7 8 9 10
Other than above
Setting prohibited
Caution When BRGC is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation. Remarks 1. fX: 2. fXX: 4. n: Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11)
3. MCS: Bit 0 of the oscillation mode select register (OSMS) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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The baud rate transmit/receive clock generated is either a signal divided from the main system clock, or a signal divided from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock from main system clock The transmit/receive clock is generated by dividing the main system clock. The baud rate generated from the main system clock is obtained from the following expression. [Baud rate] = fXX 2n x (k + 16) [Hz]
where,
fX: fXX: n: k:
Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11) Value set in MDL0 to MDL3 (0 k 14)
Table 19-5. Relationship Between Main System Clock and Baud Rate
Baud Rate (bps) fX = 5.0 MHz MCS = 1 MCS = 0 MCS = 1 fX = 4.19 MHz MCS = 0 Error (%) BRGC Set Value Error (%) 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 1.14 EBH E3H DBH CBH BBH ABH 9BH 8BH 7BH 6BH 61H 5BH -- 1.14 -2.01 1.14 1.14 1.14 1.14 1.14 1.14 1.14 1.14 -1.31 1.14 --
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value 75 110 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 76,800 06H 00H E0H D0H C0H B0H A0H 90H 80H 74H 70H 60H - 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 00H E6H E0H D0H C0H B0H A0H 90H 80H 70H 64H 60H 50H 1.73 0.88 1.73 1.73 1.73 1.73 1.73 1.73 1.73 1.73 0 1.73 1.73 0BH 03H EBH DBH CBH BBH ABH 9BH 8BH 7BH 71H 6BH 5BH
Remark
MCS: Bit 0 of the oscillation mode select register (OSMS)
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(ii) Generation of baud rate transmit/receive clock from external clock input from ASCK pin The transmit/receive clock is generated by dividing the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained from the following expression. [Baud rate] = where, fASCK 2 x (k + 16) [Hz]
fASCK: Frequency of clock input to ASCK pin k: Value set in MDL0 to MDL3 (0 k 14)
Table 19-6. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Baud Rate (bps) 75 110 150 300 600 1,200 2,400 4,800 9,600 19,200 31,250 38,400 ASCK Pin Input Frequency 2.4 kHz 3.52 kHz 4.8 kHz 9.6 kHz 19.2 kHz 38.4 kHz 76.8 kHz 153.6 kHz 307.2 kHz 614.4 kHz 1,000.0 kHz 1,228.8 kHz
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(e) Serial interface pin select register (SIPS) SIPS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SIPS to 00H. To select the input/output pins, the port mode register and the output latch of the port must be set. For details, see Table 19-2 Operating Mode Settings of Serial Interface Channel 2.
Symbol SIPS 7 0 6 0 5 4 3 0 2 0 1 0 0 0 Address FF75H After reset 00H R/W R/W
SIPS21 SIPS20
SIPS21 SIPS20 0 0 1 1 0 1 0 1
Selection of input/output pin of asynchronous serial interface Input pin: RxD0/SI2/P70 Output pin: TxD0/SO2/P71 Input pin: RxD1/BUSY/P24 Output pin: TxD0/SO2/P71 Input pin: RxD0/SI2/P70 Output pin: TxD1/STB/P23 Input pin: RxD1/BUSY/P24 Output pin: TxD1/STB/P23
Cautions 1. Select the input/output pins after stopping serial transmission/reception. 2. When using the busy control option or busy & strobe control option in the 3-wire serial I/O mode with automatic transmit/receive function of serial interface channel 1, the RxD1/ BUSY/P24 and TxD1/STB/P23 pins cannot be used as data I/O pins. 3. SIPS21 is valid only when the TXE flag is "1" and SIPS20 is valid only when the RXE flag is "1". 4. There are restrictions when SIPS21 = 1 (when the TxD1 pin is used as an output pin for UART transmission). For details, see 19.4.5 Restrictions in UART mode 2.
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(2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-8. Figure 19-8. Format of Asynchronous Serial Interface Transmit/Receive Data
One data frame
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity bit
Stop bit
Character bit
One data frame consists of the following bits: * Start bits .................. * Character bits ......... * Parity bits ................ * Stop bits .................. 1 bit 7 bits/8 bits Even parity/odd parity/0 parity/no parity 1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out by the asynchronous serial interface mode register (ASIM). When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always "0". The serial transfer rate is selected by means of ASIM and the baud rate generator control register (BRGC). If a serial data receive error occurs, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (ASIS).
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(b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a 1-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected. (i) Even parity * Transmission The number of bits with a value of "1", including the parity bit, in the transmit data is controlled to be even. The value of the parity bit is as follows: Number of bits with a value of "1" in transmit data is odd: 1
Number of bits with a value of "1" in transmit data is even: 0 * Reception The number of bits with a value of "1", including the parity bit, in the receive data is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Conversely to the situation with even parity, the number of bits with a value of "1", including the parity bit, in the transmit data is controlled to be odd. The value of the parity bit is as follows: Number of bits with a value of "1" in transmit data is odd: 0
Number of bits with a value of "1" in transmit data is even: 1 * Reception The number of bits with a value of "1", including the parity bit, in the receive data is counted. If it is even, a parity error occurs. (iii) 0 Parity When transmitting, the parity bit is set to "0" irrespective of the transmit data. At reception, a parity bit check is not performed. Therefore, a parity error does not occur, irrespective of whether the parity bit is set to "0" or "1". (iv) No parity A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error does not occur.
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(c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated. Figure 19-9. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing (a) Stop bit length: 1
STOP TxD0 (TxD1) (output) START INTST D0 D1 D2 D6 D7 Parity
(b) Stop bit length: 2
TxD0 (TxD1) (output) START INTST
D0
D1
D2
D6
D7
Parity
STOP
Caution Rewriting the asynchronous serial interface mode register (ASIM) should not be performed during a transmit operation. If rewriting the ASIM is performed during transmission, subsequent transmit operations may not be possible (the normal state is restored by RESET input). It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request (INTST) or the interrupt request flag (STIF) set by INTST.
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(d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, a receive operation is enabled and sampling of the RxD0 (RxD1) pin input is started. RxD0 (RxD1) pin input sampling is performed using the serial clock specified by ASIM. When the RxD0 (RxD1) pin input becomes low, the 5-bit counter of the baud rate generator (see Figure 19-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. If the RxD0 (RxD1) pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends. When one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (RXB), and a reception completion interrupt request (INTSR) is generated. If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of ASIM is cleared to 0 on occurrence of the error, INTSR is generated. If the RXE bit is reset to 0 during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB and the asynchronous serial interface status register (ASIS) are not changed, and INTSR and INTSER are not generated. Figure 19-10. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
STOP RxD0 (RxD1) (input) START INTSR D0 D1 D2 D6 D7 Parity
Caution The receive buffer register (RXB) must be read even if a receive error occurs. If RXB is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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(e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and a receive error interrupt request (INTSER) is generated. The receive error interrupt is generated faster than receive completion interrupt (INTSR). Receive error causes are shown in Table 19-7. It is possible to determine what kind of error occurred during reception by reading the contents of ASIS in the reception error interrupt servicing (see Figures 19-10 and 19-11). The contents of ASIS are reset to 0 by reading the receive buffer register (RXB) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). Table 19-7. Receive Error Causes
Receive Errors Parity error Framing error Overrun error Cause Transmission-time parity specification and reception data parity do not match Stop bit not detected Reception of next data is completed before data is read from receive register buffer
Figure 19-11. Receive Error Timing
RXD (input) START INTSRNote
D0
D1
D2
D6
D7
Parity
STOP
INTSER (when framing/ overrun error occurs)
INTSER (when parity error occurs)
Note
INTSR is not generated if a receive error occurs while bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1.
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset to 0 by reading the receive buffer register (RXB) or receiving the next data. To ascertain the error contents, ASIS must be read before reading RXB. 2. The receive buffer register (RXB) must be read even if a receive error occurs. If RXB is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely.
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(3) UART mode cautions (a) When the transmission under execution has been stopped by clearing bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) to 0, be sure to set the transmit shift register (TXS) to FFH, then set TXE to 1 before executing the next transmission. (b) When the reception under execution has been stopped by clearing bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) to 0, the status of the receive buffer register (RXB) and whether the receive completion interrupt request (INTSR) is generated differ depending on the timing at which reception is stopped. Figure 19-12 shows the timing. Figure 19-12. Status of Receive Buffer Register (RXB) and Generation of Interrupt Request (INTSR) When Reception Is Stopped
RxD0 (RxD1) pin
Parity
RXB
INTSR
<1>
<3> <2>
When RXE is cleared to 0 at the time indicated by <1>, RXB holds the previous data and does not generate INTSR. When RXE is cleared to 0 at the time indicated by <2>, RXB renews the data and does not generate INTSR. When RXE is cleared to 0 at the time indicated by <3>, RXB renews the data and generates INTSR.
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19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2). In the 3-wire serial I/O mode, the P23/STB/TxD1, P24/BUSY/RxD1 pins can be used as normal I/O ports. (1) Register setting 3-wire serial I/O mode is set by serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), and the baud rate generator control register (BRGC). (a) Serial operating mode register 2 (CSIM2) CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM2 to 00H.
Symbol
<7>
6 0
5 0
4 0
3 0
2
1
0
0
Address FF72H
After reset 00H
R/W R/W
CSIM2 CSIE2
CSIM CSCK 22
CSCK 0 1
Clock selection in 3-wire serial I/O mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output
CSIM22
First bit specification MSB LSB
0 1
CSIE2 0 1
Operation control in 3-wire serial I/O mode Operation stopped Operation enabled
Caution Be sure to clear bits 0 and 3 to 6 to 0.
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(b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. When the 3-wire serial I/O mode is selected, ASIM should be cleared to 00H.
Symbol ASIM <7> TXE <6> RXE 5 PS1 4 PS0 3 CL 2 SL 1 0 Address FF70H After reset 00H R/W R/W
ISRM SCK
SCK Clock selection in asynchronous serial interface mode 0 1 Input clock from off-chip to ASCK pin Dedicated baud rate generator output
ISRM 0 1
Control of reception completion interrupt request in case of error occurrence Reception completion interrupt request generated in case of error occurrence Reception completion interrupt request not generated in case of error occurrence
SL 0 1 1 bit
Transmit data stop bit length specification
2 bits
CL 0 1 7 bits 8 bits
Character length specification
PS1 0 0
PS0 0 1
Parity bit specification No parity 0 parity always added in transmission. No parity test in reception (parity error not generated). Odd parity Even parity
1 1
0 1
RXE 0 1
Receive operation control Receive operation stopped Receive operation enabled
TXE 0 1
Transmit operation control Transmit operation stopped Transmit operation enabled
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(c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H.
Symbol BRGC 7 6 5 4 3 2 1 0 Address FF73H After reset 00H R/W R/W
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 fSCK
Baud rate generator input clock selection 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
k
--
(Cont'd) Remark fSCK: 5-bit counter source clock k: Value set in MDL0 to MDL3 (0 k 14)
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TPS3 TPS2
TPS1 TPS0
5-bit counter source clock selection MCS = 1 MCS = 0 fX/211 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29 fX/210 (2.4 kHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz) (4.9 kHz)
n
0 0 0 0 1 1 1 1 1 1 1
0 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0
fXX/210 fXX fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 fXX/29
fX/210 fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 fX/29
(4.9 kHz) (5.0 MHz) (2.5 MHz) (1.25 MHz) (625 kHz) (313 kHz) (156 kHz) (78.1 kHz) (39.1 kHz) (19.5 kHz) (9.8 kHz)
11 1 2 3 4 5 6 7 8 9 10
Other than above
Setting prohibited
Caution When BRGC is written during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written during a communication operation. Remarks 1. fX: 2. fXX: 4. n: Main system clock oscillation frequency Main system clock frequency (fX or fX/2) Value set in TPS0 to TPS3 (1 n 11)
3. MCS: Bit 0 of the oscillation mode select register (OSMS) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select the serial clock frequency using TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency becomes the same as the source clock frequency for the 5-bit counter. (ii) When the baud rate generator is used: Select the serial clock frequency using TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1. The serial clock frequency is calculated by the following formula: fXX Serial clock frequency = n [Hz] 2 x (k + 16) Remarks 1. fX: 3. n: 4. k: Main system clock oscillation frequency Value set in TPS0 to TPS3 (1 n 11) Value set in MDL0 to MDL3 (0 k 14)
2. fXX: Main system clock frequency (fX or fX/2)
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(2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit-wise synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2) on the rise of SCK2. At the end of an 8-bit transfer, the operation of TXS/SIO2 or RXS stops automatically, and the interrupt request flag (SRIF) is set. Figure 19-13. 3-Wire Serial I/O Mode Timing
SCK2
1
2
3
4
5
6
7
8
SI2
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SRIF End of transfer Transfer start at the falling edge of SCK2
(3) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, it is possible to select transfer to start from the MSB or LSB. Figure 19-14 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown in the figure, the MSB/LSB can be read or written in reverse form. MSB/LSB switching as the start bit can be specified by bit 2 (CSIM22) of serial operating mode register 2 (CSIM2).
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Figure 19-14. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SO2 latch SI2 Transmit shift register (TXS/SIO2) D Q
SO2
SCK2
Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (4) Transfer start Serial transfer is started by setting transfer data to the transmission shift register (TXS/SIO2) when the following two conditions are satisfied.
* Serial interface channel 2 operation control bit (CSIE2) = 1 * Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.
Caution If CSIE2 is set to 1 after data write to TXS/SIO2, transfer does not start. Remark CSIE2: Bit 7 of serial operating mode register 2 (CSIM2)
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is set.
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19.4.4 Restrictions in UART mode 1 In the UART mode, the reception completion interrupt request (INTSR) is generated a certain time after the reception error interrupt (INTSER) is generated and then cleared. Consequently, the following phenomenon may occur.
*
Description If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion interrupt request (INTSR) is not generated on occurrence of a reception error. If the receive buffer register (RXB) is read at certain timing ("a" in Figure 19-15) during the reception error interrupt (INTSER) servicing, the internal error flag is cleared to 0. As a result, it is judged that no reception error has occurred, and INTSR, which should not be generated, is generated. Figure 19-15 illustrates this operation. Figure 19-15. Reception Completion Interrupt Request Generation Timing (When ISRM = 1)
fSCK
INTSER (when framing/ overrun error occurs) a Error Flag (internal flag) INTSR Interrupt processing routine of CPU Reading RXB It is judged that reception error has not occurred, and INTSR is generated Cleared on reading RXB
Remark
ISRM: Bit 1 of the asynchronous serial interface mode register (ASIM) fSCK: RXB: Source clock of 5-bit counter of baud rate generator Receive buffer register
To avoid this phenomenon, take the following measures.
*
Preventive measures * In case of framing error or overrun error Disable the receive buffer register (RXB) from being read for a certain period (T2 in Figure 19-16) after the reception error interrupt request (INTSER) has been generated. * In case of parity error Disable the receive buffer register (RXB) from being read for a certain period (T1 + T2 in Figure 19-16) after the reception error interrupt request (INTSER) has been generated.
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Figure 19-16. Receive Buffer Register Read Disable Period
RXD (input) START
D0
D1
D2
D6
D7
Parity
STOP
INTSR
INTSER (when framing/ overrun error occurs)
INTSER (when parity error occurs)
T1
T2
T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate) T2: Time of 2 clocks of source clock (fSCK) of 5-bit counter selected by BRGC
*
Example of preventive measures Here is an example of the above preventive measures. [Conditions] fX = 5.0 MHz Processor clock control register (PCC) = 00H Oscillation mode select register (OSMS) = 01H Baud rate generator control register (BRGC) = B0H (2,400 bps selected as baud rate) TCY = 0.4 s (tCY = 0.2 s) T1 = 1 2,400 = 416.7 s
T2 = 12.8 x 2 = 25.6 s T1 + T2 tCY = 2,212 (clocks)
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[Example]
Main processing
UART receive error interrupt (INTSER) servicing
EI INTSER generated Seven CPU clocks (MIN.) (time from generation of interrupt request to processing) Instructions of 2,205 CPU clocks (MIN.) are necessary.
MOV A, RXB
RETI
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19.4.5 Restrictions in UART mode 2 To use the TxD1/STB/P23 pin to output UART data by using the time-division transfer function, perform the following processing when the transmit operation is enabled and when the transmit/receive operation is stopped. The output circuit of the alternate function of this TxD1/STB/P23 pin differs between the actual device and the incircuit emulator (see Figure 19-17). Therefore, delete the underlined part in the examples below when executing emulation with the in-circuit emulator (IE). Condition: Serial interface pin select register (SIPS) = 20H or 30H (when using TxD1 pin as output pin for UART transmission) (1) When transmit operation is enabled
CLR1 SET1 SET1 CLR1 MOV PM2.3 P2.3 ASIM.7 P2.3 TXS, #BYTE ; Sets P23 (TXD1) pin to output mode. ; Sets output latch of P23 to "1". ; Enables transmission (TXE = 1). ; This line is necessary only for the actual device. Delete it when the IE is used. ; Transfers transmit data (#BYTE) to transmit shift register.
Cautions 1. Perform this processing each time a transmit operation is enabled by using the TxD1 pin as an output pin. 2. Perform this processing each time the output pin is switched from the TxD0 pin to the TxD1 pin because the transmit operation must be stopped once and then enabled again. (2) When transmit operation is stopped
SET1 CLR1 P2.3 ASIM.7 ; This line is necessary only for the actual device. Delete it when the IE is used. ; Stops transmission (TXE = 0).
Cautions 1. Perform this processing each time a transmit operation is enabled by using the TxD1 pin as an output pin. 2. Perform this processing each time the output pin is switched from the TxD0 pin to the TxD1 pin because the transmit operation must be stopped once and then enabled again. Figure 19-17. P23 Output Selector
Alternate output signal (TxD1) (Actual device) Output latch of P23 PM23
P23/STB/TxD1
(In-circuit emulator)
Alternate output signal (TxD1) Output latch of P23 PM23
P23/STB/TxD1
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CHAPTER 20 REAL-TIME OUTPUT PORT
20.1 Real-Time Output Port Functions
Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with the generation of a timer interrupt request or external interrupt request, then output externally. This is called the real-time output function. The pins that output data externally are called real-time output ports. By using a real-time output, a signal which has no jitter can be output. This port is therefore suitable for control of stepper motors, etc. Port mode/real-time output port mode can be specified in 1-bit units.
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20.2 Real-Time Output Port Configuration
The real-time output port consists of the following hardware. Table 20-1. Real-Time Output Port Configuration
Item Register Control registers Configuration Real-time output buffer register (RTBL, RTBH) Port mode register 12 (PM12) Real-time output port mode register (RTPM) Real-time output port control register (RTPC)
Figure 20-1. Real-Time Output Port Block Diagram
Internal bus Real-time output port control register BYTE EXTR Port mode register 12 (PM12)
INTP2 INTTM1 INTTM2 Output trigger controller
Real-time output buffer register higher 4 bits (RTBH)
Real-time output buffer register lower 4 bits (RTBL) Real-time output port mode register (RTPM)
Output latch
P127
P120
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(1) Real-time output buffer registers (RTBL, RTBH) The addresses of RTBL and RTBH are mapped individually in the special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits x 2 channels as the operating mode, data is set individually to RTBL and RTBH. When specifying 8 bits x 1 channel as the operating mode, data is set to both RTBL and RTBH by writing 8bit data to either RTBL or RTBH. Table 20-2 shows the operations during manipulation of RTBL and RTBH. Figure 20-2. Real-Time Output Buffer Register Configuration
Higher 4 bits FF30H FF31H RTBH Lower 4 bits RTBL
Table 20-2. Operation in Real-Time Output Buffer Register Manipulation
Operating Mode Register to Be Manipulated RTBL RTBH 8 bits x 1 channel RTBL RTBH ReadingNote 1 Higher 4 Bits RTBH RTBH RTBH RTBH Lower 4 Bits RTBL RTBL RTBL RTBL WritingNote 2 Higher 4 Bits Invalid RTBH RTBH RTBH Lower 4 Bits RTBL Invalid RTBL RTBL
4 bits x 2 channels
Notes 1. Only the bits set in the real-time output port mode can be read. When a bit set in the port mode is read, 0 is read. 2. After setting data in the real-time output port, output data should be set to RTBL and RTBH by the time a real-time output trigger is generated.
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20.3 Real-Time Output Port Control Registers
The following three registers control the real-time output port. * Port mode register 12 (PM12) * Real-time output port mode register (RTPM) * Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of the port 12 pins (P120 to P127) which function alternately as real-time output pins (RTP0 to RTP7). To use port 12 as a real-time output port, the port pin that performs real-time output must be set in the output mode (PM12n = 0: n = 0 to 7). PM12 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM12 to FFH. Figure 20-3. Format of Port Mode Register 12
Symbol
7
6
5
4
3
2
1
0
Address FF2CH
After reset FFH
R/W R/W
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PM12n 0 1
Selection of I/O mode of P12n pin (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
(2) Real-time output port mode register (RTPM) This register selects the real-time output port mode/port mode in 1-bit units. RTPM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears RTPM to 00H. Figure 20-4. Format of Real-Time Output Port Mode Register
Symbol 7 6 5 4 3 2 1 0 Address FF34H RTPMn 0 1 After reset 00H R/W R/W
RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0
Real-time output port selection (n = 0 to 7) Port mode Real-time output port mode
Cautions 1. When using these bits as a real-time output port, set the ports at which real-time output is performed to the output mode (clear the corresponding bit of port mode register 12 (PM12) to 0). 2. In ports specified as real-time output ports, data cannot be set to the output latch. Therefore, when setting an initial value, data should be set to the output latch before setting the real-time output mode.
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(3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relationship between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears RTPC to 00H. Figure 20-5. Format of Real-Time Output Port Control Register
Symbol RTPC
7 0
6 0
5 0
4 0
3 0
2 0
<1>
<0>
Address FF36H EXTR 0 1
After reset 00H
R/W R/W
BYTE EXTR
Real-time output control by INTP2 INTP2 not specified as real-time output trigger INTP2 specified as real-time output trigger
BYTE 0 1
Real-time output port operating mode 4 bits x 2 channels 8 bits x 1 channel
Table 20-3. Real-Time Output Port Operating Mode and Output Trigger
BYTE 0 EXTR 0 1 1 0 1 8 bits x 1 channel Operating Mode 4 bits x 2 channels RTBH Port Output INTTM2 INTTM1 INTTM1 INTP2 RTBL Port Output INTTM1 INTP2
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21.1 Interrupt Function Types
The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal. One interrupt source from the watchdog timer is provided as a non-maskable interrupt source. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L). High-priority interrupts can be given priority over to low priority interrupts by using multiple interrupt servicing. If two or more interrupts with the same priority are generated simultaneously, each interrupt has a predetermined priority (see Table 21-1). A standby release signal is generated. Six external interrupt sources and thirteen internal interrupt sources are provided as maskable interrupt sources. (3) Software interrupt This is a vectored interrupt that occurs when the BRK instruction is executed. It is acknowledged even in a disabled state. The software interrupt does not undergo interrupt priority control.
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21.2 Interrupt Sources and Configuration
A total of 21 non-maskable, maskable, and software interrupts are provided as interrupt sources (see Table 21-1). Table 21-1. Interrupt Source List (1/2)
Interrupt Type Nonmaskable Maskable Default PriorityNote 1 -- Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H End of serial interface channel 0 transfer End of serial interface channel 1 transfer Occurrence of serial interface channel 2 UART reception error End of serial interface channel 2 UART reception End of serial interface channel 2 3-wire transfer End of serial interface channel 2 UART transfer 001CH Internal 0014H (B) Internal/ External Internal Vector Table Address 0004H Basic Configuration TypeNote 2 (A)
0
INTWDT
(B)
1 2 3 4 5 6 7
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0
(C) (D)
8
INTCSI1
0016H
9
INTSER
0018H
10
INTSR
001AH
INTCSI2
11
INTST
Notes 1. The default priority is the priority used when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority and 17 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 21-1.
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Table 21-1. Interrupt Source List (2/2)
Interrupt Type Maskable Default PriorityNote 1 12 Interrupt Source Name INTTM3 Trigger Reference time interval signal from watch timer Generation of 16-bit timer register, capture/compare register 00 (CR00) match signal Generation of 16-bit timer register, capture/compare register 01 (CR01) match signal Generation of 8-bit timer/event counter 1 match signal Generation of 8 bit timer/event counter 2 match signal End of A/D converter conversion BRK instruction execution -- Internal/ External Internal Vector Table Address 001EH Basic Configuration TypeNote 2 (B)
13
INTTM00
0020H
14
INTTM01
0022H
15
INTTM1
0024H
16
INTTM2
0026H
17 Software --
INTAD BRK
0028H 003EH (E)
Notes 1. The default priority is the priority used when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority and 17 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 21-1.
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Figure 21-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
Priority controller IF
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority controller
Vector table address generator Standby release signal
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Figure 21-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0)
Internal bus
External interrupt mode register (INTM0, INTM1)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator
Remark
IF: IE: MK: PR:
Interrupt request flag Interrupt enable flag Interrupt mask flag Priority specification flag
ISP: Inservice priority flag
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21.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specification flag register (PR0L, PR0H, PR1L) * External interrupt mode register (INTM0, INTM1) * Sampling clock select register (SCS) * Program status word (PSW) Table 21-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 21-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Register INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0 INTCSI1 INTSER INTSR/INTCSI2 INTST INTTM3 INTTM00 INTTM01 INTTM1 INTTM2 INTAD TMIF4 PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 CSIIF0 CSIIF1 SERIF SRIF STIF TMIF3 TMIF00 TMIF01 TMIF1 TMIF2 ADIF IF0H IF0L TMMK4 PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 CSIMK0 CSIMK1 SERMK SRMK STMK TMMK3 TMMK00 TMMK01 TMMK1 TMMK2 ADMK MK0H Interrupt Mask Flag Register MK0L TMPR4 PPR0 PPR1 PPR2 PPR3 PPR4 PPR5 CSIPR0 CSIPR1 SERPR SRPR STPR TMPR3 TMPR00 TMPR01 TMPR1 TMPR2 ADPR PR0H Priority Specification Flag Register PR0L
IF1L
MK1L
PR1L
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or an 8-bit memory manipulation instruction. If IF0L and IF0H are used as the 16-bit register IF0, use a 16-bit memory manipulation instruction for setting. RESET input clears these registers to 00H. Figure 21-2. Format of Interrupt Request Flag Register
Address FFE0H After reset 00H R/W R/W
Symbol IF0L
7 0 <7>
<6> PIF5 <6>
<5> PIF4 <5>
<4> PIF3 <4>
<3> PIF2 <3>
<2> PIF1 <2>
<1>
<0>
PIF0 TMIF4 <1> <0>
IF0H TMIF01 TMIF00 TMIF3 STIF SRIF SERIF CSIIF1 CSIIF0 <7> IF1L WTIF
Note
FFE1H
00H
R/W
6 0
5 0
4 0
3 0
<2>
<1>
<0> FFE2H 00H R/W
ADIF TMIF2 TMIF1
x x IFx 0 1
Interrupt request flag No interrupt request signal Interrupt request signal is generated; interrupt request state
Note
WTIF is the test input flag. A vectored interrupt request is not generated.
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If the watchdog timer is used in watchdog timer mode 1, clear the TMIF4 flag to 0. 2. Be sure to clear IF0L bit 7 and IF1L bits 3 to 6 to 0. 3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then servicing of the interrupt routine is started.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or an 8-bit memory manipulation instruction. If MK0L and MK0H are used as the 16-bit register MK0, use a 16-bit memory manipulation instruction for setting. RESET input sets these registers to FFH. Figure 21-3. Format of Interrupt Mask Flag Register
Symbol MK0L
7 1 <7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FFE4H
After reset FFH
R/W R/W
PMK5 PMK4 PMK3 PMK2 PMK <6> <5> <4> <3> <2>
PMK TMMK4 <1> <0>
MK0H TMMK01 TMMK00 TMMK3 STMK SRMK SERMK CSIMK1 CSIMK0 <7> MK1L WTMK
Note
FFE5H
FFH
R/W
6 1
5 1
4 1
3 1
<2>
<1>
<0> FFE6H FFH R/W
ADMK TMMK2 TMMK1
x x MK x 0 1
Interrupt servicing control Interrupt servicing enabled Interrupt servicing disabled
Note
WTMK controls standby mode release enable/disable; it does not control the interrupt function.
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1, the MK0 value becomes undefined. 2. Because port 0 also functions as an external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. Be sure to set MK0L bit 7 and MK1L bits 3 to 6 to 1.
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(3) Priority specification flag registers (PR0L, PR0H, and PR1L) The priority specification flags are used to set the corresponding maskable interrupt priorities. PR0L, PR0H, and PR1L are set with a 1-bit or an 8-bit memory manipulation instruction. If PR0L and PR0H are used as the 16-bit register PR0, use a 16-bit memory manipulation instruction for setting. RESET input sets these registers to FFH. Figure 21-4. Format of Priority Specification Flag Register
Symbol PR0L 7 1 <7> <6> <5> <4> <3> <2> <1> <0> Address FFE8H After reset FFH R/W R/W
PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 TMPR4 <6> <5> <4> <3> <2> <1> <0>
PR0H TMPR01 TMPR00 TMPR3 STPR SRPR SERPR CSIPR1 CSIPR0 7 PR1L 1 6 1 5 1 4 1 3 1 <2> <1> <0>
FFE9H
FFH
R/W
ADPR TMPR2 TMPR1
FFEAH
FFH
R/W
x x PR x 0 1
Priority level selection High priority level Low priority level
Cautions 1. If the watchdog timer is used in watchdog timer mode 1, set the TMPR4 flag to 1. 2. Be sure to set PR0L bit 7 and PR1L bits 3 to 7 to 1.
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(4) External interrupt mode registers (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP5, TI00, and TI01. INTM0 specifies the valid edges of interrupt pins INTP0 to INTP2, TI00, and TI01, and INTM1 specifies the valid edges of INTP3 to INTP5. INTM0 and INTM1 are set with an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 21-5. Format of External Interrupt Mode Register 0
Symbol 7 6 5 4 3 2 1 0 0 0 Address FFECH After reset 00H R/W R/W
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
ES11 ES10 0 0 1 1 0 1 0 1
INTP0/TI00 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES21 ES20 0 0 1 1 0 1 0 1
INTP1/TI01 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES31 ES30 0 0 1 1 0 1 0 1
INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
Caution When using the TI00/P00/INTP0 and TI01/P01/INTP1 pins as timer input pins (TI00 and TI01), stop the operation of 16-bit timer 0 by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI00 and TI01. The valid edge is set by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0). When using the TI00/P00/INTP0 and TI01/P01/INTP1 pins as external interrupt input pins (INTP0 and INTP1), the valid edge of INTP0 and INTP1 may be set while 16-bit timer 0 is operating.
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Figure 21-6. Format of External Interrupt Mode Register 1
Symbol INTM1 7 0 6 0 5 4 3 2 1 0 Address FFEDH After reset 00H R/W R/W
ES61 ES60 ES51 ES50 ES41 ES40
ES41 ES40 0 0 1 1 0 1 0 1
INTP3 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES51 ES50 0 0 1 1 0 1 0 1
INTP4 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
ES61 ES60 0 0 1 1 0 1 0 1
INTP5 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges
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(5) Sampling clock select register (SCS) This register is used to set the clock for sampling the valid edge input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is eliminated using the sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input clears SCS to 00H. Figure 21-7. Format of Sampling Clock Select Register
Address FF47H After reset 00H R/W R/W
Symbol SCS
7 0
6 0
5 0
4 0
3 0
2 0
1
0
SCS1 SCS0
SCS1 SCS0
INTP0 sampling clock selection MCS = 1 MCS = 0
0 0 1 1
0 1 0 1
fXX/2 fXX/2 fXX/2
N 7 5
fX/27 (39.1 kHz)
fX/2 (19.5 kHz)
8
fX/25 (156.3 kHz) fX/26 (78.1 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz)
fXX/26
Caution fXX/2N is the clock supplied to the CPU and fXX/25, fXX/26, and fXX/27 are clocks supplied to the peripheral hardware. fXX/2N stops in the HALT mode. Remarks 1. N: 2. fXX: 3. fX: Value (N = 0 to 4) of bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC) Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
4. MCS: Bit 0 of the oscillation mode select register (OSMS) 5. Values in parentheses apply to operation with fX = 5.0 MHz.
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When the sampled INTP0 input level is the active level twice in succession, the noise eliminator sets the interrupt request flag (PIF0) to 1. Figure 21-8 shows the I/O timing of the noise eliminator. Figure 21-8. Noise Eliminator I/O Timing (During Rising Edge Detection) (a) When input is less than the sampling cycle (tSMP)
tSMP Sampling clock
INTP0
PIF0
"L" Because the INTP0 level is not high when it is sampled, PIF0 output remains at low level.
(b) When input is equal to or twice the sampling cycle (tSMP)
tSMP Sampling clock
INTP0
<1>
<2>
PIF0 Because the sampled INTP0 level is high twice in succession in <2>, the PIF0 flag is set to 1.
(c) When input is more than twice the cycle frequency (tSMP)
tSMP Sampling clock
INTP0
PIF0 Because the INTP0 level is high twice in succession, the PIF0 flag is set to 1.
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(6) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status of an interrupt request. The IE flag, which sets maskable interrupt enable/disable, and the ISP flag, which controls multiple interrupt servicing, are mapped to the PSW. Besides 8-bit unit read/write, this register can also be manipulated by a bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK instruction is executed, the contents of the PSW are automatically saved to the stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The contents of the PSW can also be saved into the stack with the PUSH PSW instruction. The contents are reset from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets the PSW to 02H. Figure 21-9. Format of Program Status Word
7 PSW IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being received High-priority interrupt servicing (low-priority interrupts disabled) Interrupt request not acknowledged or low-priority interrupt servicing (all maskable interrupts enabled)
1
IE 0 1
Interrupt request acknowledge enable/disable Disabled Enabled
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21.4 Interrupt Servicing Operations
21.4.1 Non-maskable interrupt request acknowledgment operation A non-maskable interrupt request is unconditionally acknowledged even if interrupt requests are in an acknowledgment disabled state. It does not undergo interrupt priority control and has the highest priority of all interrupts. If a non-maskable interrupt request is acknowledged, the contents of the acknowledged interrupt are saved in the stack, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into the PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. Figure 21-10 shows the flowchart illustrating how a non-maskable interrupt request occurs and is acknowledged. Figure 21-11 shows the acknowledgment timing of a non-maskable interrupt request. Figure 21-12 shows the acknowledgment operation of multiple non-maskable interrupt requests.
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Figure 21-10. Non-Maskable Interrupt Request Occurrence and Acknowledgment Flowchart
Start
WDTM4 = 1 (with watchdog timer mode selected)? Yes
No Interval timer
Overflow in WDT?
No
Yes WDTM3 = 0 (with non-maskable interrupt selected)? No Reset processing Yes Interrupt request generation
WDT interrupt servicing?
No Interrupt request held pending
Yes
Interrupt control register unaccessed?
No
Yes Interrupt servicing start
WDTM: Watchdog timer mode register WDT: Watchdog timer
Figure 21-11. Non-Maskable Interrupt Request Acknowledgment Timing
CPU instruction
Instruction
Instruction
PSW and PC save, jump to interrupt servicing
Interrupt servicing program
TMIF4
An interrupt request generated during this period is acknowledged at the timing marked . TMIF4 : Watchdog timer interrupt request flag
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Figure 21-12. Non-Maskable Interrupt Request Acknowledgment Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> NMI request <2> 1 instruction execution
NMI request <1> execution NMI request <2> held pending
Pending NMI request <2> serviced
(b)
If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> 1 instruction execution
NMI request <2> NMI request <3>
NMI request <1> execution NMI request <2> held pending NMI request <3> held pending
Pending NMI request <2> serviced
NMI request <3> is not acknowledged (NMI request is acknowledged only once even if it occurs twice or more).
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21.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request becomes acknowledgeable when the corresponding interrupt request flag is set to 1 and the corresponding interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enabled state (with the IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt servicing (with the ISP flag reset to 0). Wait times from maskable interrupt request generation to interrupt servicing are shown in Table 21-3. For the timing to acknowledge an interrupt request, see Figures 21-14 and 21-15. Table 21-3. Times from Maskable Interrupt Request Generation to Interrupt Servicing
Minimum Time When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum TimeNote 32 clocks 33 clocks
Note
If an interrupt request is generated just before a divide instruction, the wait time becomes the maximum.
Remark
1 clock:
1 (fCPU: CPU clock) fCPU
If two or more maskable interrupt requests are generated simultaneously, the request specified as higher priority with the priority specification flag is acknowledged first. If two or more requests specified as the same priority by the interrupt priority specification flag are generated simultaneously, the one with the higher default priority is acknowledged first. Any pending interrupt requests are acknowledged when they become acknowledgeable. Figure 21-13 shows an interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents of acknowledged interrupt are saved in the stack, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged interrupt priority specification flag contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into the PC and branched. Restoration from the interrupt is possible with the RETI instruction.
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Figure 21-13. Interrupt Request Acknowledgment Processing Algorithm
Start
No
x x IF = 1?
Yes (Interrupt request generation)
No
x x MK = 0?
Yes
Interrupt request held pending
Yes (high priority)
x x PR = 0?
No (low priority)
Yes
Interrupt request held pending No
Any highpriority interrupt among simultaneously generated xxPR = 0 interrupt requests? No
Any simultaneously generated xxPR = 0 interrupt requests? No Any simultaneously generated high-priority interrupt requests? No
Yes Interrupt request held pending
IE = 1?
Yes Vectored interrupt servicing
Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending
Interrupt request held pending
IE = 1?
Yes
ISP = 1?
Yes Vectored interrupt servicing
xxIF:
Interrupt request flag
xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag that controls maskable interrupt request acknowledge (1 = enable, 0 = disable) Flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority is being serviced. 1 = interrupt request is not acknowledged or interrupt with low priority being serviced).
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Figure 21-14. Interrupt Request Acknowledgment Timing (Minimum Time)
6 clocks
PSW and PC save, jump to interrupt servicing Interrupt servicing program
CPU processing
Instruction
Instruction
x x IF (x x PR = 1) 8 clocks x x IF (x x PR = 0) 7 clocks
Remark
1 clock:
1 (fCPU: CPU clock) fCPU
Figure 21-15. Interrupt Request Acknowledgment Timing (Maximum Time)
25 clocks 6 clocks
PSW and PC save, jump to interrupt servicing Interrupt servicing program
CPU processing
Instruction
Divide instruction
x x IF (x x PR = 1) 33 clocks x x IF (x x PR = 0) 32 clocks
Remark
1 clock:
1 (fCPU: CPU clock) fCPU
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21.4.3 Software interrupt request acknowledgment operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents of the acknowledged interrupt are saved in the stack, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into the PC and branched. Restoration from the software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for restoring from the software interrupt. 21.4.4 Multiple interrupt servicing Acknowledging another interrupt request while one interrupt is being serviced is called multiple interrupt servicing. Multiple interrupt servicing does not occur unless interrupt requests are enabled (IE = 1) (except the non-maskable interrupt). When an interrupt request is acknowledged, the other interrupts are disabled (IE = 0). To enable multiple interrupt servicing, therefore, the IE flag must be set to 1 by executing the EI instruction during interrupt servicing and interrupts must be enabled. Even if interrupt requests are enabled, multiple interrupt servicing may not be possible. However, this is controlled by the programmable priority. An interrupt has two types of priorities: the default priority and the programmable priority. Multiple interrupt servicing is controlled by the programmable priority. In the EI status, if an interrupt request with a priority that is the same or higher than that of the interrupt currently being serviced is generated, the interrupt is acknowledged for multiple interrupt servicing. If an interrupt request with a priority lower than that of the interrupt currently being serviced is generated, the interrupt is not acknowledged for multiple interrupt servicing. If interrupts are disabled, or if multiple interrupt servicing is not enabled because the interrupt has a low priority, the interrupt is held pending. After the servicing of the current interrupt has been completed, and after one instruction of the main processing has been executed, the pending interrupt is acknowledged. Multiple interrupt servicing is not enabled while a non-maskable interrupt is being serviced. Table 21-4 shows the interrupt requests enabled for multiple interrupt servicing. Figure 21-16 shows multiple interrupt servicing examples. Table 21-4. Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing
Multiple Interrupt Non-maskable Request Interrupt Request Interrupt Being Serviced Non-maskable interrupt Maskable interrupt ISP = 0 ISP = 1 Software interrupt D E E E Maskable Interrupt Request PR = 0 IE = 1 D E E E IE = 0 D D D D PR = 1 IE = 1 D D E E IE = 0 D D D D
Remarks 1. E: Multiple interrupt servicing enabled 2. D: Multiple interrupt servicing disabled 3. ISP and IE are flags contained in the PSW ISP = 0: An interrupt with a higher priority is being serviced ISP = 1: An interrupt request is not acknowledged or an interrupt with a lower priority is being serviced IE = 0: IE = 1: Interrupt request acknowledgment is disabled Interrupt request acknowledgment is enabled
4. PR is a flag contained in PR0L, PR0H, and PR1L PR = 0: Higher priority level PR = 1: Lower priority level
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Figure 21-16. Multiple Interrupt Servicing Example (1/2) Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing IE = 0 EI EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 0 EI INTyy servicing IE = 0 INTzz servicing
INTxx (PR = 1)
RETI
RETI
Two interrupt requests, INTyy and INTzz, are acknowledged while the INTxx interrupt is being serviced. Before each interrupt request is acknowledged, the EI instruction is always issued and interrupt requests are enabled. Example 2. Multiple interrupt servicing does not occur because of interrupt priority
Main processing INTxx servicing INTyy servicing
EI
IE = 0 EI INTyy (PR = 1) RETI
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI
INTyy, which occurs while INTxx is being serviced is not acknowledged for multiple interrupt servicing because the priority of INTyy is lower than that of INTxx. INTyy is held pending and is acknowledged after one instruction of the main processing has been executed. PR = 0: PR = 1: IE = 0: High-priority interrupt Low-priority interrupt Interrupt acknowledgment disabled
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Figure 21-16. Multiple Interrupt Servicing Example (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing IE = 0 INTyy (PR = 0) RETI
INTyy servicing
EI
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI
In the servicing of INTxx, other interrupts are not enabled (the EI instruction is not executed). Therefore, INTyy is not acknowledged for multiple interrupt servicing. This interrupt is held pending and acknowledged after one instruction of the main processing has been executed. PR = 0: IE = 0: High-priority interrupt Interrupt acknowledgment disabled
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21.4.5 Interrupt request pending For some instructions, even if an interrupt is generated while that instruction is being executed, the interrupt is held pending until execution of the next instruction is completed. The instructions that hold interrupt requests pending (interrupt request pending) are shown below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW.bit, CY * MOV1 CY, PSW.bit * AND1 CY, PSW.bit * OR1 CY, PSW.bit * XOR1 CY, PSW.bit * SET1 PSW.bit * CLR1 PSW.bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW.bit, $addr16 * BF PSW.bit, $addr16 * BTCLR PSW.bit, $addr16 * EI * DI * Manipulation instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers Caution The BRK instruction is not an interrupt request pending instruction. However, the IE flag is cleared to 0 by a software interrupt that is started by BRK instruction execution. Thus, even if a maskable interrupt request is generated during BRK instruction execution, that interrupt request is not acknowledged. However, a non-maskable interrupt request is acknowledged. Figure 21-17 shows the timing at which an interrupt request is held pending. Figure 21-17. Interrupt Request Pending Timing
CPU processing
Instruction N
Instruction M
Save PSW and PC, jump to interrupt servicing
Interrupt servicing program
x x IF
Remarks 1. Instruction N: Instruction that holds interrupts requests pending 2. Instruction M: Instructions other than instruction N 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
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21.5 Test Function
When the watch timer overflows and the port 4 falling edge is detected, the internal test input flag is set to 1, and the standby release signal is generated. Unlike the interrupt function, vectored processing is not performed. There are two test input sources as shown in Table 21-5. The basic configuration is shown in Figure 21-18. Table 21-5. Test Input Sources
Test Input Sources Name INTWT INTPT4 Trigger Watch timer overflow Falling edge detection at port 4 Internal/ External Internal External
Figure 21-18. Basic Configuration of Test Function
Internal bus
MK
Test input signal
IF
Standby release signal
Remark IF: Test input flag MK: Test mask flag 21.5.1 Registers controlling test function The test function is controlled by the following three registers. * Interrupt request flag register 1L (IF1L) * Interrupt mask flag register 1L (MK1L) * Key return mode register (KRM) The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table 21-6. Table 21-6. Flags Corresponding to Test Input Signals
Test Input Signal Name INTWT INTPT4 Test Input Flag WTIF KRIF Test Mask Flag WTMK KRMK
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(1) Interrupt request flag register 1L (IF1L) This register indicates whether a watch timer overflow is detected or not. IF1L is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF1L to 00H. Figure 21-19. Format of Interrupt Request Flag Register 1L
Address FFE2H After reset 00H R/W R/W
Symbol
<7>
6 0
5 0
4 0
3 0
<2>
<1>
<0>
IF1L WTIF
ADIF TMIF2 TMIF1
WTIF 0 1
Watch timer overflow detection flag Not detected Detected
Caution Be sure to clear bits 3 to 6 to 0. (2) Interrupt mask flag register 1L (MK1L) This register is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer. MK1L is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK1L to FFH. Figure 21-20. Format of Interrupt Mask Flag Register 1L
Address FFE6H After reset FFH R/W R/W
Symbol
<7>
6 1
5 1
4 0
3 0
<2>
<1>
<0>
MK1L WTMK
ADMK TMMK2 TMMK1
WTMK 0 1
Standby mode control by watch timer Releasing the standby mode enabled Releasing the standby mode disabled
Caution Be sure to set bits 3 to 6 to 1.
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(3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by the key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H. Figure 21-21. Format of Key Return Mode Register
Symbol KRM 7 0 6 0 5 0 4 0 3 0 2 0 <1> <0> Address FFF6H After reset 02H R/W R/W
KRMK KRIF
KRIF 0 1 Not detected
Key return signal
Detected (port 4 falling edge detection)
KRMK 0 1
Standby mode control by key return signal Standby mode release enabled Standby mode release disabled
Caution When port 4 falling edge detection is used, be sure to clear KRIF to 0 (it is not cleared to 0 automatically). 21.5.2 Test input signal acknowledgment operation (1) Internal test signal (INTWT) INTWT is generated when the watch timer overflows, and sets the WTIF flag. Unless interrupts are masked by the interrupt mask flag (WTMK) at this time, the standby release signal is generated. The watch function is realized by checking the WTIF flag at a shorter cycle than the watch timer overflow cycle. (2) External test input signal (INTPT4) INTPT4 is generated when a falling edge is input to the port 4 pins (P40 to P47), and KRIF is set. Unless interrupts are masked by the interrupt mask flag (KRMK) at this time, the standby release signal is generated. If port 4 is used as a key matrix return signal input, whether or not a key input has been applied can be checked from the KRIF status.
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EXTERNAL DEVICE EXPANSION FUNCTION
22.1 External Device Expansion Function
The external device expansion function connects external devices to areas other than the internal ROM, RAM, and SFR. Ports 4 to 6 are used for connection of external devices. Ports 4 to 6 control addresses/data, the read/ write strobe, wait, address strobe etc. Table 22-1. Pin Functions in External Memory Expansion Mode
Pin Function When External Device Is Connected Name AD0 to AD7 A8 to A15 RD WR WAIT ASTB Function Multiplexed address/data bus Address bus Read strobe signal Write strobe signal Wait signal Address strobe signal P40 to P47 P50 to P57 P64 P65 P66 P67 Alternate Function
Table 22-2. State of Port 4 to 6 Pins in External Memory Expansion Mode
Ports and Bits External Expansion Modes Single-chip mode 256-byte expansion mode 4 KB expansion mode 16 KB expansion mode Full-address mode Port Address/data Address/data Address/data Address/data Port 4 0 to 7 0 1 2 Port 5 3 4 5 6 7 0 to 3 Port Port Port Port Port Port Port Port RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB RD, WR, WAIT, ASTB Port 6 4 to 7
Port Port Address Address Address
Caution
When the external wait function is not used, the WAIT pin can be used as a port in all modes.
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Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map When Using External Device Expansion Function (1/3) (a) Memory map of PD780053 and 780053Y, and PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y with internal ROM (flash memory) set to 24 KB
FFFFH SFR FF00H FEFFH FF00H FEFFH
(b) Memory map of PD780054 and 780054Y, and PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y with internal ROM (flash memory) set to 32 KB
FFFFH SFR
Internal high-speed RAM
Internal high-speed RAM
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved FA80H FA7FH
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved FA80H FA7FH
Full-address mode (when MM2 to MM0 = 111)
Full-address mode (when MM2 to MM0 = 111)
A000H 9FFFH 16 KB expansion mode (when MM2 to MM0 = 101) 7000H 6FFFH 6100H 60FFH 6000H 5FFFH
C000H BFFFH 16 KB expansion mode (when MM2 to MM0 = 101) 9000H 8FFFH 8100H 80FFH 8000H 7FFFH
4 KB expansion mode (when MM2 to MM0 = 100) 256-byte expansion mode (when MM2 to MM0 = 011)
4 KB expansion mode (when MM2 to MM0 = 100) 256-byte expansion mode (when MM2 to MM0 = 011)
Single-chip mode
Single-chip mode
0000H
0000H
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Figure 22-1. Memory Map When Using External Device Expansion Function (2/3) (c) Memory map of PD780055 and 780055Y, and PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y with internal ROM (flash memory) set to 40 KB
FFFFH SFR FF00H FEFFH
(d) Memory map of PD780056 and 780056Y, and PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y with internal ROM (flash memory) set to 48 KB
FFFFH SFR FF00H FEFFH
Internal high-speed RAM
Internal high-speed RAM
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved FA80H FA7FH Full-address mode (when MM2 to MM0 = 111) E000H DFFFH 16 KB expansion mode (when MM2 to MM0 = 101) B000H AFFFH A100H A0FFH A000H 9FFFH 4 KB expansion mode (when MM2 to MM0 = 100) 256-byte expansion mode (when MM2 to MM0 = 011)
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved FA80H FA7FH Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) D000H CFFFH 4 KB expansion mode (when MM2 to MM0 = 100) C100H C0FFH C000H BFFFH
256-byte expansion mode (when MM2 to MM0 = 011)
Single-chip mode
Single-chip mode
0000H
0000H
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Figure 22-1. Memory Map When Using External Device Expansion Function (3/3) (e) PD780058, 780058B, 780058BY, 78F0058, 78F0058Y Memory map when internal ROM (flash memory) size is 56 KB (f) PD780058, 780058B, 780058BY, 78F0058, 78F0058Y Memory map when internal ROM (flash memory) size is 60 KB
FFFFH SFR FF00H FEFFH
FFFFH SFR FF00H FEFFH
Internal high-speed RAM
Internal high-speed RAM
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved F800H F7FFH Internal expansion RAM F400H F3FFH Full-address mode (when MM2 to MM0 = 111) or 16 KB expansion mode (when MM2 to MM0 = 101) F000H EFFFH E100H F0FFH E000H DFFFH
FB00H FAFFH Reserved FAE0H FADFH Internal buffer RAM FAC0H FABFH Reserved F800H F7FFH Internal expansion RAM F400H F3FFH
Reserved
4 KB expansion mode (when MM2 to MM0 = 100) 256-byte expansion mode (when MM2 to MM0 = 011)
F000H EFFFH
Single-chip mode Single-chip mode
0000H
0000H
Caution When the internal ROM (flash memory) size is 60 KB, the area from F000H to F3FFH cannot be used. F000H to F3FFH can be used as external memory by setting the internal ROM (flash memory) size to 56 KB or less using the internal memory size switching register (IMS).
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22.2
External Device Expansion Function Control Register
The external device expansion function is controlled by the memory expansion mode register (MM) and internal memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output mode of port 4. MM is set with a 1-bit memory or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 22-2. Format of Memory Expansion Mode Register
Symbol MM 7 0 6 0 5 PW1 4 PW0 3 0 2 MM2 1 0 Address FFF8H After reset 10H R/W R/W
MM1 MM0
MM2 MM1
MM0
Single-chip/ memory expansion mode selection Single-chip mode
P40 to P47, P50 to P57, P64 to P67 pin state P40 to P47 P50 to P53 P54, P55 Port Input Port mode mode
Output
P56, P57
P64 to P67
0 0 0
0 0 1
0 1 1
1 1 1
0 0 1
0 1 1
Memory 256-byte expansion mode mode 4 KB mode 16 KB mode Fulladdress Note mode Setting prohibited
AD0 to AD7 Port mode
A8 to A11
Port mode
A12, A13
P64 = RD P65 = WR P66 = WAIT Port mode P67 = ASTB A14, A15
Other than above
PW1 0 0 1 1
PW0 0 1 0 1 No wait Wait (one wait state insertion) Setting prohibited Wait control by external wait pin
Wait control
Note
The full-address mode allows external expansion to the entire 64 KB address space except for the internal ROM, RAM, and SFR areas and the reserved areas.
Remark
P60 to P63 are used as port pins without regard to the mode (single-chip mode or memory expansion mode).
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(2) Internal memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in the default status. However, when using the external device expansion function with the PD780058, 780058B, and 780058BY, set IMS so that the internal ROM capacity is 56 KB or less. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to the value indicated in Table 22-3. Figure 22-3. Format of Internal Memory Size Switching Register
Symbol 7 6 5 4 0 3 2 1 0
Address FFF0H
After reset Note
R/W R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1
Internal ROM size selection 24 KB 32 KB 40 KB 48 KB 56 KB 60 KB Setting prohibited
Other than above
RAM2 RAM1 RAM0 Internal high-speed RAM size selection 1 1 0 1,024 bytes Setting prohibited
Other than above
Note
The values after reset depend on the product (see Table 22-3). Table 22-3. Values After Internal Memory Size Switching Register Is Reset
Part Number Reset Value C6H C8H CAH CCH CFH
PD780053, 780053Y PD780054, 780054Y PD780055, 780055Y PD780056, 780056Y PD780058, 780058B, 780058BY
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22.3 External Device Expansion Function Timing
The timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (alternate function: P64) Read strobe signal output pin. The read strobe signal is output upon the occurrence of data accesses and instruction fetches from external memory. During internal memory access, the read strobe signal is not output (maintains high level). (2) WR pin (alternate function: P65) Write strobe signal output pin. The write strobe signal is output upon the occurrence of data access to external memory. During internal memory access, the write strobe signal is not output (maintains high level). (3) WAIT pin (alternate function: P66) External wait signal input pin. When the external wait is not used, the WAIT pin can be used as an I/O port. During internal memory access, the external wait signal is ignored. (4) ASTB pin (alternate function: P67) Address strobe signal output pin. The ASTB signal is output without regard to data accesses and instruction fetches from external memory. The ASTB signal is also output when the internal memory is accessed. (5) AD0 to AD7, A8 to A15 pins (alternate function: P40 to P47, P50 to P57) Address/data signal output pin. A valid signal is output or input during data accesses and instruction fetches from external memory. These signals change when the internal memory is accessed (output values are undefined). The timing charts are shown in Figures 22-4 to 22-7.
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Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting
ASTB RD AD0 to AD7 A8 to A15 Lower address Operation code
Higher address
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB RD AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait) Lower address Operation code Higher address
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB RD
AD0 to AD7
Lower address
Operation code
A8 to A15 WAIT
Higher address
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Figure 22-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting
ASTB RD AD0 to AD7 A8 to A15 Lower address Read data Higher address
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB RD AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait) Lower address Read data Higher address
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB RD
AD0 to AD7
Lower address
Read data
A8 to A15 WAIT
Higher address
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Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting
ASTB WR AD0 to AD7 A8 to A15 Lower address Hi-Z Higher address Write data
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB WR AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Lower address
Hi-Z Higher address
Write data
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB WR AD0 to AD7 A8 to A15 WAIT
Lower address
Hi-Z
Write data Higher address
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Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting
ASTB RD WR AD0 to AD7 A8 to A15 Lower address Read data Hi-Z Higher address Write data
(b) Wait (PW1, PW0 = 0, 1) setting
ASTB RD WR AD0 to AD7 A8 to A15 Internal wait signal (1-clock wait)
Lower address
Read data
Hi-Z Higher address
Write data
(c) External wait (PW1, PW0 = 1, 1) setting
ASTB RD WR AD0 to AD7 A8 to A15 WAIT
Lower address
Read data
Hi-Z
Write data
Higher address
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22.4 Example of Connection with Memory
Figure 22-8 shows an example of the connection between the PD780054 and external memory. SRAM is used as the external memory in this diagram. In addition, the external device expansion function is used in the full-address mode, and the addresses from 0000H to 7FFFH (32 KB) are allocated to internal ROM, and the addresses after 8000H to SRAM. Figure 22-8. Example of Connection Between PD780054 and Memory
PD780054
VDD
PD43256B
CS
RD WR
OE WE I/O1 to I/O8 Data bus
A8 to A14 74HC573 ASTB LE Q0 to Q7 AD0 to AD7 D0 to D7 OE Address bus
A0 to A14
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STANDBY FUNCTION
23.1 Standby Function and Configuration
23.1.1 Standby function The standby function is designed to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is used to stop the CPU operation clock. The system clock oscillator continues oscillating. In this mode, the current consumption cannot be decreased as much as in the STOP mode, but the HALT mode is effective for restarting immediately upon interrupt request and to carry out intermittent operations such as in watch applications. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops. The CPU current consumption can be considerably decreased. Data memory low-voltage hold (down to VDD = 1.8 V) is possible. Thus, the STOP mode is effective for holding data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure oscillation stabilization after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In any mode, all the contents of the registers, flags and data memory just before standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the system operates on the main system clock (subsystem clock oscillation cannot be stopped). The HALT mode can be used with either the main system clock or the subsystem clock. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before executing the STOP instruction. 3. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: first clear bit 7 (CS) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction.
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23.1.2 Standby function control register The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. However, it takes 217/fX, not 218/fX, until the STOP mode is released by RESET input. Figure 23-1. Format of Oscillation Stabilizat Time Select Register
Symbol OSTS 7 0 6 0 5 0 4 0 3 0 2 1 0 Address FFFAH After reset 04H R/W R/W
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0
Selection of oscillation stabilization time when STOP mode is released MCS = 1 MCS = 0 212/fXX 212/fX (819 s)
13 2 /fX (1.64 ms)
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
14 14 15 2 /fXX 2 /fX (3.28 ms) 2 /fX (6.55 ms) 15 15 16 2 /fXX 2 /fX (6.55 ms) 2 /fX (13.1 ms) 16 16 17 2 /fXX 2 /fX (13.1 ms) 2 /fX (26.2 ms)
217/fXX 217/fX (26.2 ms) 218/fX (52.4 ms)
Other than above Setting prohibited
Caution The wait time that elapses when the STOP mode is released does not include the time required for the clock to start oscillation (see "a" in the illustration below) after the STOP mode is released. The same applies when the STOP mode is released by RESET input and by generation of an interrupt request.
STOP mode release X1 pin voltage waveform a
Remarks 1. fXX: 2. fX:
Main system clock frequency (fX or fX/2) Main system clock oscillation frequency
3. MCS: Bit 0 of the oscillation mode select register (OSMS) 4. Values in parentheses apply to operation with fX = 5.0 MHz
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23.2 Standby Function Operations
23.2.1 HALT mode (1) HALT mode setting and operating status The HALT mode is set by executing the HALT instruction. It can be set when using either the main system clock or the subsystem clock. The operating status in the HALT mode is described below. Table 23-1. HALT Mode Operating Status
Setting of HALT Mode On Execution of HALT Instruction During Main System Clock Operation Without subsystem clockNote 1 With subsystem clock Note 2 On Execution of HALT Instruction during Subsystem Clock Operation When main system clock continues oscillation When main system clock stops oscillation
Item Clock generator CPU Ports (output latches) 16-bit timer/event counter
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops. Operation stops Status before HALT mode setting is held Operable Operable when watch timer output is selected as count clock (fXT is selected as count clock of watch timer) or when TI00 is selected Operable when TI1 or TI2 is selected as count clock Operable Operation stops Operation stops Operable when fXT is selected as count clock
8-bit timer/event counter
Operable
Watch timer Watchdog timer A/D converter D/A converter Real-time output port Serial interface Other than automatic transmit/ receive function Automatic transmit/ receive function External interrupt requests INTP0 INTP1 to INTP5 Bus line for external expansion AD0 to AD7 A0 to A15 ASTB WR, RD WAIT
Operable when fXX/27 is selected as count clock Operable Operable Operable Operable Operable
Operable when external SCK is used
Operation stops
INTP0 is operable when clock supplied for peripheral hardware is selected as sampling clock (fXX/25, fXX/26, fXX/27) Operable High impedance Status before HALT mode setting is held Low level High level High impedance
Operation stops
Notes 1. Including when an external clock is not supplied 2. Including when an external clock is supplied
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(2) HALT mode release The HALT mode can be released by the following four types of sources. (a) Release by unmasked interrupt request If an unmasked interrupt request is generated, the HALT mode is released. instruction is executed. Figure 23-2. HALT Mode Release by Interrupt Request Generation If interrupt request acknowledgment is enabled, vectored interrupt servicing is carried out. If disabled, the next address
HALT instruction Standby release signal Operating mode
Interrupt request
Wait
HALT mode Oscillation
Wait
Operating mode
Clock
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby status is acknowledged. 2. The wait time will be as follows: * When the program branches to the vector table: 8 to 9 clocks * When the program does not branch to the vector table: 2 to 3 clocks (b) Release by non-maskable interrupt request generation If a non-maskable interrupt request is generated, the HALT mode is released and vectored interrupt servicing is carried out irrespective of whether interrupt request acknowledgment is enabled or disabled. (c) Release by unmasked test input If an unmasked test signal is input, the HALT mode is released, and the next address instruction of the HALT instruction is executed.
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(d) Release by RESET input If the RESET signal is input, the HALT mode is released. As is the case with a normal reset operation, the program is executed after branch to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input
Wait (217/fX : 26.2 ms)
HALT Instruction RESET signal Operating mode Reset period
Oscillation stop
HALT mode Oscillation
Oscillation stabilization wait status Oscillation
Operating mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 5.0 MHz. Table 23-2. Operation After HALT Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Non-maskable interrupt request Test input - PRxx 0 0 1 1 1 x - IE 0 1 0 x 1 x x x x x ISP x x 1 0 1 x x x x x Interrupt servicing execution HALT mode hold Interrupt servicing execution Operation Next address instruction execution Interrupt servicing execution Next address instruction execution
0 1
- - -
Next address instruction execution HALT mode hold Reset processing
RESET input
-
Remark
x: don't care
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23.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. It can be set only when using the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait time set using the oscillation stabilization time select register (OSTS) elapses, the operating mode is set. The operating status in the STOP mode is described below. Table 23-3. STOP Mode Operating Status
Setting of STOP Mode Item Clock generator CPU Ports (output latches) 16-bit timer/event counter With Subsystem Clock Only main system clock stops oscillation Operation stops Status before STOP mode setting is held Operable when watch timer output is selected as count clock (fXT is selected as count clock of watch timer) Operation stops Without Subsystem Clock
8-bit timer/event counter Watch timer Watchdog timer A/D converter D/A converter Real-time output port Serial interface Other than automatic transmit/receive function and UART Automatic transmit/receive function and UART External interrupt requests Bus line for external expansion INTP0 INTP1 to INTP5 AD0 to AD7 A0 to A15 ASTB WR, RD WAIT
Operable when TI1 and TI2 are selected for the count clock Operable when fXT is selected for the count clock Operation stops Operation stops
Operable Operable when external trigger is used or TI1 and TI2 are selected for the 8-bit timer/event counter count clock Operable when externally supplied clock is specified as the serial clock
Operation stops
Not operable Operable High impedance Status before STOP mode setting is held Low level High level High impedance
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(2) STOP mode release The STOP mode can be released by the following three types of sources. (a) Release by unmasked interrupt request If an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. If interrupt request acknowledgment is disabled, the next address instruction is executed. Figure 23-4. STOP Mode Release by Interrupt Request Generation
Wait (time set by OSTS)
STOP instruction Standby release signal Operating mode Oscillation
Interrupt request
STOP mode Oscillation stop
Oscillation stabilization wait status Oscillation
Operating mode
Clock
Remark The broken lines indicate the case when the interrupt request which has released the standby status is acknowledged.
(b) Release by unmasked test input If an unmasked test signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, the instruction at the next address of the STOP instruction is executed.
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(c) Release by RESET input If the RESET signal is input, the STOP mode is released and after the lapse of oscillation stabilization time, a reset operation is carried out. Figure 23-5. STOP Mode Release by RESET Input
Wait (217/fX : 26.2 ms)
STOP instruction RESET signal Operating mode Oscillation Clock Reset period
STOP mode Oscillation stop
Oscillation stabilization wait status Oscillation
Operating mode
Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 5.0 MHz. Table 23-4. Operation After STOP Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Test input 0 1 RESET input - PRxx 0 0 1 1 1 x - - - IE 0 1 0 x 1 x x x x ISP x x 1 0 1 x x x x Interrupt servicing execution STOP mode hold Next address instruction execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt servicing execution Next address instruction execution
Remark x: don't care
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24.1 Reset Function
The following two operations are available to generate a reset signal. (1) External reset input by RESET pin (2) Internal reset by watchdog timer program loop time detection The external reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware unit is set to the status shown in Table 24-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset is released. When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figures 24-2 to 244). Cautions 1. For an external reset, input a low level to the RESET pin for 10 s or more. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pin becomes high impedance. Figure 24-1. Reset Function Block Diagram
RESET
Reset controller
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
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Figure 24-2. Reset Timing by RESET Input
X1 Normal operation Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing)
RESET Internal reset signal
Delay Delay Port pin Hi-Z
Figure 24-3. Reset Timing due to Watchdog Timer Overflow
X1 Normal operation Watchdog timer overflow Internal reset signal Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing)
Port pin
Hi-Z
Figure 24-4. Reset Timing by RESET Input in STOP Mode
X1
STOP instruction execution Stop status (oscillation stop) Reset period (oscillation stop) Oscillation stabilization time wait
Normal operation RESET Internal reset signal
Normal operation (reset processing)
Delay Port pin
Delay Hi-Z
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Table 24-1. Hardware Status After Reset (1/2)
Hardware Program counter (PC)Note 1 Status After Reset The contents of the reset vector tables (0000H and 0001H) are set. Undefined 02H Data memory General register Ports (output latches) Ports 0 to 3, 7, 12, 13 (P0 to P3, P7, P12, P13) Ports 4 to 6 (P4 to P6) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) Pull-up resistor option registers (PUOH, PUOL) Processor clock control register (PCC) Oscillation mode select register (OSMS) Internal memory size switching register (IMS) Internal expansion RAM size switching register (IXS)Note 4 Memory expansion mode register (MM) Oscillation stabilization time select register (OSTS) 16-bit timer/event counter Timer register (TM0) Capture/compare registers (CR00, CR01) Clock select register (TCL0) Mode control register (TMC0) Capture/compare control register 0 (CRC0) Output control register (TOC0) 8-bit timer/event counters 1 and 2 Timer register (TM1, TM2) Compare registers (CR10, CR20) Clock select register (TCL1) Mode control registers (TMC1) Output control register (TOC1) UndefinedNote 2 UndefinedNote 2 00H
Stack pointer (SP) Program status word (PSW) RAM
Undefined FFH 00H 04H 00H
Note 3
0AH 10H 04H 00H Undefined 00H 00H 04H 00H 00H Undefined 00H 00H 00H
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. If the reset signal is input in the standby mode, the status before reset is retained even after reset. 3. The values after reset depend on the product.
PD780053, 780053Y: C6H, PD780054, 780054Y: C8H, PD780055, 780055Y: CAH, PD780056, 780056Y: CCH, PD780058, 780058B, 780058BY: CFH, PD78F0058, 78F0058Y: CFH
4. Provided only in the PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y.
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Table 24-1. Hardware Status After Reset (2/2)
Hardware Watch timer Watchdog timer Serial interface Mode control register (TMC2) Clock select register (TCL2) Mode register (WDTM) Clock select register (TCL3) Shift registers (SIO0, SIO1) Mode registers (CSIM0, CSIM1, CSIM2) Serial bus interface control register (SBIC) Slave address register (SVA) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive address pointer (ADTP) Automatic data transmit/receive interval specification register (ADTI) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Serial interface pin select register (SIPS) Transmit shift register (TXS) Receive buffer register (RXB) Interrupt timing specification register (SINT) A/D converter Mode register (ADM) Conversion result register (ADCR) Input select register (ADIS) D/A converter Mode register (DAM) Conversion value setting registers (DACS0, DACS1) Real-time output port Mode register (RTPM) Control register (RTPC) Buffer registers (RTBL, RTBH) ROM correctionNote Correction address registers (CORAD0, CORAD1) Correction control register (CORCN) Interrupts Request flag registers (IF0L, IF0H, IF1L) Mask flag registers (MK0L, MK0H, MK1L) Priority specification flag registers (PR0L, PR0H, PR1L) External interrupt mode registers (INTM0, INTM1) Key return mode register (KRM) Sampling clock select register (SCS) 00H 01H Undefined 00H 00H 00H 00H 00H 00H 0000H 00H 00H FFH FFH 00H 02H 00H Status After Reset 00H 00H 00H 88H Undefined 00H 00H Undefined 00H 00H 00H 00H 00H 00H 00H FFH
Note
Provided only in the PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y.
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25.1 ROM Correction Function
The PD780058, 780058B, 780058BY, 78F0058, 78F0058Y can replace part of a program in the mask ROM or flash memory with a program in the internal expansion RAM. Instruction bugs found in the mask ROM or flash memory can be avoided, and program flow can be changed by using the ROM correction function. The ROM correction function can be used to correct two places (max.) of the internal ROM or flash memory (program). Cautions 1. ROM correction can be used only for the PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y. 2. ROM correction function cannot be emulated by the in-circuit emulator (IE-78000-R, IE-78000R-A, IE-78K0-NS, IE-78K0-NS-A, IE-78001-R-A).
25.2 ROM Correction Configuration
The ROM correction function consists of the following hardware. Table 25-1. ROM Correction Configuration
Item Registers Control register Configuration Correction address registers 0, 1 (CORAD0, CORAD1) Correction control register (CORCN)
Figure 25-1 shows a block diagram of the ROM correction function. Figure 25-1. ROM Correction Block Diagram
Program counter (PC)
Comparator
Match
Correction branch request signal (BR !F7FDH)
Correction address register (CORADn)
CORENn CORSTn Correction control register Internal bus
Remark
n = 0, 1
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(1) Correction address registers 0, 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM or flash memory. The ROM correction function corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1. If only one place needs to be corrected, set the address to either of the registers. CORAD0 and CORAD1 are set with a 16-bit memory manipulation instruction. RESET input clears CORAD0 and CORAD1 to 0000H. Figure 25-2. Format of Correction Address Registers 0 and 1
Symbol CORAD0 15 0 Address FF38H/FF39H After reset 0000H R/W R/W
CORAD1
FF3AH/FF3BH
0000H
R/W
Cautions 1. Set CORAD0 and CORAD1 when bit 1 (COREN0) and bit 3 (COREN1) of the correction control register (CORCN: See Figure 25-3) are 0. 2. Only addresses where operation codes are stored can be set to CORAD0 and CORAD1. 3. Do not set the following addresses to CORAD0 and CORAD1. * Address value in table area of table reference instruction (CALLT instruction): 0040H to 007FH * Address value in vector table area: 0000H to 003FH (2) Comparator The comparator continuously compares the correction address value set in correction address registers 0 and 1 (CORAD0, CORAD1) with the fetch address value. When bit 1 (COREN0) or bit 3 (COREN1) of the correction control register (CORCN) is 1 and the correction address matches the fetch address value, the correction branch request signal (BR !F7FDH) is generated from the ROM correction circuit.
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25.3 ROM Correction Control Registers
The ROM correction function is controlled by the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. The correction control register consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The correction enable flags enable or disable the comparator match detection signal, and correction status flags show that the values match. CORCN is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CORCN to 00H. Figure 25-3. Format of Correction Control Register
Symbol CORCN 7 0 6 0 5 0 4 0 <3> <2> <1> <0> Address FF8AH After reset 00H R/W R/WNote
COREN1 CORST1 COREN0 CORST0
CORST0 Correction address register 0 and fetch address match detection 0 1 Not detected Detected
COREN0 Correction address register 0 and fetch address match detection control 0 1 Disabled Enabled
CORST1 Correction address register 1 and fetch address match detection 0 1 Not detected Detected
COREN1 0 1
Correction address register 1 and fetch address match detection control Disabled Enabled
Note
Bits 0 and 2 are read-only bits.
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25.4 ROM Correction Application
(1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROMTM) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address registers 0 and 1 (CORAD0 or CORAD1) generates the correction branch. Figure 25-4. Example of Storing to EEPROM (When One Place Is Corrected)
EEPROM
00H 01H 02H 00 10 0D 02 9B 02 10 RA78K/0
Source program
CSEG AT 1000H ADD BR A, #2 !1002H
FFH
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(2) Assemble in advance the initialization routine as shown in Figure 25-5 to correct the program. Figure 25-5. Initialization Routine
Initialization ROM correction
Is ROM correction used?Note Yes Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction operation enabled
No
Main program
Note
Whether the ROM correction function is used or not should be judged by the port input level. For example, when the P20 input level is high, ROM correction is used, otherwise, it is not used.
(3) After reset, store the contents that were previously stored in the external nonvolatile memory by the user initialization routine for ROM correction to internal expansion RAM (see Figure 25-5). Set the start address of the instruction to be corrected to CORAD0 and CORAD1, and set bits 1 and 3 (COREN0, COREN1) of the correction control register (CORCN) to 1. (4) Set the entire-space branch instruction (BR !addr16) to the specified address (F7FDH) of the internal expansion RAM using the main program. (5) After the main program is started, the fetch address value and the values set in CORAD0 and CORAD1 are continuously compared by the comparator in the ROM correction circuit. When these values match, the correction branch request signal is generated. Simultaneously the corresponding correction status flag (CORST0 or CORST1) is set to 1. (6) Branch to the address F7FDH via the correction branch request signal. (7) Branch to the internal expansion RAM address set by the main program via the entire-space branch instruction of the address F7FDH. (8) When one place is corrected, the correction program is executed. When two places are corrected, the correction status flag is checked by the branch destination judgment program, and the program branches to the correction program.
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Figure 25-6. ROM Correction Operation
Internal ROM (flash memory) program start
Does fetch address match correction address? Yes
No
ROM correction
Set correction status flag
Correction branch (branch to address F7FDH)
Correction program execution
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25.5 ROM Correction Usage Example
An example of ROM correction when the instruction at address 1000H "ADD A, #1" is changed to "ADD A, #2" is shown below. Figure 25-7. ROM Correction Usage Example
Internal ROM or flash memory 0000H 0080H Program start
Internal expansion RAM F400H
F702H (3) 1000H 1002H ADD A, #1 MOV B, A (1)
ADD A, #2 BR !1002H (2)
F7FDH BR !F702H F7FFH
EFFFH
(1) The program branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch address value after the main program is started. (2) The program branches to any address (address F702H in this example) by setting the entire-space branch instruction (BR !addr16) to address F7FDH by the main program. (3) The program returns to the internal ROM (flash memory) program after executing the substitute instruction ADD A, #2.
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25.6 Program Execution Flow
Figures 25-8 and 25-9 show the program transition diagrams when the ROM correction is used. Figure 25-8. Program Transition Diagram (When One Place Is Corrected)
FFFFH F7FFH BR !JUMP F7FDH (2)
Correction program JUMP
(1) (3) Internal ROM
Correction place xxxxH Internal ROM (flash memory) 0000H
(1) The program branches to address F7FDH when the fetch address matches the correction address (2) The program branches to the correction program (3) The program returns to the internal ROM (flash memory) program Remark Shaded area: Internal expansion RAM JUMP: Correction program start address
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Figure 25-9. Program Transition Diagram (When Two Places Are Corrected)
FFFFH F7FFH BR !JUMP F7FDH Correction program 2 yyyyH Correction program 1 xxxxH Destination judge program JUMP (4) (3) (8) (7) (2) (6)
Internal ROM (flash memory) Correction place 2 Internal ROM (flash memory) Correction place 1 Internal ROM (flash memory) 0000H (1)
(5)
(1) The program branches to address F7FDH when the fetch address matches the correction address (2) The program branches to the branch destination judgment program (3) The program branches to correction program 1 via the branch destination judgment program (BTCLR !CORST0, $xxxxH) (4) The program returns to the internal ROM (flash memory) program (5) The program branches to address F7FDH when the fetch address matches the correction address (6) The program branches to the branch destination judgment program (7) The program branches to correction program 2 via the branch destination judgment program (BTCLR !CORST1, $yyyyH) (8) The program returns to the internal ROM (flash memory) program Remark Shaded Area: Internal expansion RAM JUMP: Destination judge program start address
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25.7 ROM Correction Cautions
(1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in the disabled state). If an address is set to CORAD0 or CORAD1 when COREN0 or COREN1 is 1 (when the correction branch is in the enabled state), the correction branch may start with a different address from the set address value. (3) Do not set the address value of an instruction immediately after the instruction that sets the correction enable flag (COREN0, COREN1) to 1, to correction address register 0 or 1 (CORAD0, CORAD1); otherwise the correction branch may not start. (4) Do not set the address value in the table area of the table reference instruction (CALLT instruction) (0040H to 007FH), and the address value in the vector table area (0000H to 003FH) to correction address registers 0 and 1 (CORAD0, CORAD1). (5) Do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 (CORAD0, CORAD1). (That is, when the mapped terminal address of these instructions is N, do not set the address values of N + 1 and N + 2.) * RET * RETI * RETB * BR $addr16 * STOP * HALT
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CHAPTER 26 PD78F0058, 78F0058Y
The PD78F0058 and 78F0058Y have flash memory whose contents can be written, erased, rewritten with the device mounted on a PC board. Table 26-1 lists the differences between the flash memory versions (PD78F0058 and 78F0058Y) and the mask ROM versions (PD780053, 780054, 780055, 780056, 780058, 780058B, 780053Y, 780054Y, 780055Y, 780056Y, and 780058BY). Table 26-1. Differences Between PD78F0058, 78F0058Y and Mask ROM Versions
Item
PD78F0058
PD78F0058Y
Mask ROM Versions
PD780058 Subseries
Internal ROM structure Internal ROM capacity Flash memory 60 KB Mask ROM
PD780058Y Subseries
PD780053, PD780054, PD780055, PD780056, PD780058, PD780053, PD780054, PD780055, PD780056, PD780058,
780053Y: 780054Y: 780055Y: 780056Y: 780058B, 780053Y: 780054Y: 780055Y: 780056Y: 780058B,
24 KB 32 KB 40 KB 48 KB 780058BY: 60 KB None None None None 780058BY: 1,024 bytes
Internal expansion RAM capacity
1,024 bytes
Internal ROM capacity changeable/not changeable using internal memory size switching register (IMS) Internal expansion RAM capacity changeable/not changeable using interna expansion RAM size switching register (IXS) Supply voltage IC pin VPP pin P60 to P63 pin mask option with on-chip pull-up resistors Serial interface (SBI) Serial interface (I C)
2
ChangeableNote 1
Not changeable
ChangeableNote 2
Not changeable
VDD = 2.7Note 3 to 5.5 V Not provided Provided Not provided Provided Not provided Not provided Provided
VDD = 1.8 to 5.5 V Provided Not provided Provided Provided Not provided Not provided Provided
Notes 1. Flash memory is set to 60 KB by RESET input. 2. Internal expansion RAM is set to 1,024 bytes by RESET input. 3. VDD = 2.2 V can also be supplied. Contact an NEC Electronics sales representative for details. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. Remark Only the PD780058, 780058B, 78F0058, 780058BY, and 78F0058Y are provided with an internal expansion RAM size switching register.
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26.1 Internal memory Size Switching Register
The PD78F0058 and 78F0058Y allow users to define the internal ROM size using the internal memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal ROM is possible. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 26-1. Format of Memory Size Switching Register
Symbol 7 6 5 4 0 3 2 1 0 Address FFF0H After reset CFH R/W R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 24 KB 32 KB 40 KB 48 KB 56 KBNote 60 KB Setting prohibited
Other than above
RAM2 RAM1 RAM0 Internal high-speed RAM capacity selection 1 1 0 1,024 bytes Setting prohibited
Other than above
Note
When using the external device expansion function of the PD780058, 780058B, 780058BY, 78F0058, and 78F0058Y, set the internal ROM capacity to 56 KB or less.
The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-2. Table 26-2. Internal Memory Size Switching Register Setting Values
Target Mask ROM Version IMS Setting Value C6H C8H CAH CCH CFH
PD780053, 780053Y PD780054, 780054Y PD780055, 780055Y PD780056, 780056Y PD780058, 780058B, 780058BY
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26.2 Internal Expansion RAM Size Switching Register
The PD78F0058 and 78F0058Y allow users to define the internal expansion RAM size by using the internal expansion RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different-size internal expansion RAM is possible. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 26-2. Format of Internal Expansion RAM Size Switching Register
Symbol IXS
7 0
6 0
5 0
4 0
3
2
1
0
Address FFF4H
After reset 0AH
R/W W
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal extension RAM capacity selection 1 1 1 0 0 1 0 0 0 bytes 1,024 bytes Setting prohibited
Other than above
The IXS settings that give the same memory map as the mask ROM versions are shown in Table 26-3. Table 26-3. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Version IXS Setting Value 0CH
PD780053, 780053Y PD780054, 780054Y PD780055, 780055Y PD780056, 780056Y PD780058, 780058B, 780058BY
0AH
Remark If a program for the PD78F0058 or 78F0058Y which includes "MOV IXS, #0CH" is implemented with the PD780053, 780053Y, 780054, 780054Y, 780055, 780055Y, 780056, or 780056Y, this instruction is ignored and causes no malfunction.
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26.3 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FLPR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board). A flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR3, FL-PR4, and the program adapter are products of Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities low-quantity, varied model production * Easy data adjustment when starting mass production 26.3.1 Programming environment The following shows the environment required for PD78F0058, 78F0058Y flash memory programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 26-3. Environment for Writing Program to Flash Memory
VPP RS-232C USB Dedicated flash programmer Host machine VDD VSS RESET SIO/UART/PORT
PD78F0058, PD78F0058Y
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26.3.2 Communication mode Use the communication mode shown in Table 26-4 to perform communication between the dedicated flash programmer and PD78F0058, 78F0058Y. Table 26-4. Communication Mode List
Communication Mode COMM PORT SIO Clock TYPE SettingNote 1 CPU CLOCK Optional Flash Clock Multiple Rate 1.0 P27/SCK0/SCL P26/SO0/SB1/SDA1 P25/SI0/SB0/SDA0 P22/SCK1 P21/SO1 P20/SI1 SIO ch-2 (3 wired, sync.) P72/SCK2/ASCK P71/SO2/TxD0 P70/SI2/RxD0 UART (UART0) UART ch-0 (Async.) UART ch-1 (Async.) Pseudo 3-wire serial I/O Port A (Pseudo-3 wired) 100 Hz to 1 kHz Optional 1 to 5 MHzNote 2 1.0 4,800 to 76,800 bpsNotes 2, 3 Optional 1 to 5 MHzNote 2 1.0 P71/SO2/TxD0 P70/SI2/RxD0 P23/TxD1 P24/RxD1 P32/TO2 (Serial clock I/O) P31/TO1 (Serial data output) P30/TO0 (Serial data input) 9 8 2 Pins Used Number of VPP Pulses 0
3-wire serial I/O SIO ch-0 (3 wired, sync.)
100 Hz to 1.25 MHzNote 2
1 to 5 MHzNote 2
SIO ch-1 (3 wired, sync.)
1
12
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, see CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION), CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V). 3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. Figure 26-4. Communication Mode Selection Format
VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash memory write mode
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Figure 26-5. Example of Connection with Dedicated Flash Programmer (1/2) (a) 3-wire serial I/O (SIO ch-0)
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLKNote GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1, AVREF RESET SCK0 SI0 SO0 X1 VSS0, VSS1, AVSS
(b) 3-wire serial I/O (SIO ch-1)
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLKNote GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1, AVREF RESET SCK1 SI1 SO1 X1 VSS0, VSS1, AVSS
(c) 3-wire serial I/O (SIO ch-2)
PD78F0058, 78F0058Y
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK
Note
VPP VDD0, VDD1, AVREF RESET SCK2 SI2 SO2 X1 VSS0, VSS1, AVSS
GND
Note
Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator is already connected to the X1 pin, the CLK pin does not need to be connected.
Caution The VDD0 and VDD1 pins, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD0 and VDD1 pins, supply voltage before starting programming.
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Figure 26-5. Example of Connection with Dedicated Flash Programmer (2/2) (d) UART (UART ch-0)
Dedicated flash programmer VPP1 VDD RESET SO (TXD) SI (RXD) CLKNote GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1, AVREF RESET RXD0 TXD0 X1 VSS0, VSS1, AVSS
(e) UART (UART ch-1)
Dedicated flash programmer VPP1 VDD RESET SO (TXD) SI (RXD) CLKNote GND
PD78F0058, 78F0058Y
VPP VDD0, VDD1, AVREF RESET RXD1 TXD1 X1 VSS0, VSS1, AVSS
(f) Pseudo 3-wire serial I/O
Dedicated flash programmer VPP1 VDD RESET SCK SO SI CLK
Note
PD78F0058, 78F0058Y
VPP VDD0, VDD1, AVREF RESET P32 P30 P31 X1 VSS0, VSS1, AVSS
GND
Note
Connect this pin when the system clock is supplied from the dedicated flash programmer. If a resonator is already connected to the X1 pin, the CLK pin does not need to be connected.
Caution The VDD0 and VDD1 pins, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD0 and VDD1 pins, supply voltage before starting programming.
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If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the PD78F0058, 78F0058Y. For details, refer to the manual of Flashpro III/Flashpro IV. Table 26-5. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART Pseudo 3-Wire Serial I/O
VPP1 VPP2 VDD
Output - I/O - Output Output Input Output Output Input
Write voltage - VDD voltage generation/ voltage monitoring Ground Clock output Reset signal Reception signal Transmit signal Transfer clock Handshake signal
VPP - VDD0, VDD1, AVREF x
Note
x
Note
x
Note
GND CLK RESET SI (RxD) SO (TxD) SCK HS
VSS0, VSS1, AVSS X1 RESET SO0/SO1/SO2/TxD0/TxD1/P31 SI0/SI1/SI2/RxD0/RxD1/P30 SCK0/SCK1/SCK2/P32 - x x x x x
Note
VDD voltage must be supplied before programming is started. : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. x: Pin does not need to be connected.
Remark
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26.3.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform the following. (1) Connect a pull-down resistor (RVPP = 10 k) to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND. A VPP pin connection example is shown below. Figure 26-6. VPP Pin Connection Example
PD78F0058, 78F0058Y
Connection pin of dedicated flash programmer VPP
Pull-down resistor (RVPP)
The following shows the pins used by the serial interface.
Serial Interface 3-wire serial I/O Pins Used SI0, SO0, SCK0 SI1, SO1, SCK1 SI2, SO2, SCK2 UART RxD0, TxD0 RxD1, TxD1 Pseudo 3-wire serial I/O P30, P31, P32
When connecting the dedicated flash programmer to a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such connections.
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(1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 26-7. Signal Conflict (Input Pin of Serial Interface)
PD78F0058, 78F0058Y
Signal conflict Input pin
Connection pin of dedicated flash programmer Other device Output pin
In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device.
(2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. Figure 26-8. Abnormal Operation of Other Device
PD78F0058, 78F0058Y
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the PD78F0058, 78F0058Y affects another device in the flash memory programming mode, isolate the signals of the other device.
PD78F0058, 78F0058Y
Connection pin of dedicated flash programmer Other device Input pin
Pin
If the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device.
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If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 26-9. Signal Conflict (RESET Pin)
PD78F0058, 78F0058Y
Signal conflict RESET
Connection pin of dedicated flash programmer Reset signal generator Output pin
The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator.
When the PD78F0058 and 78F0058Y enter the flash memory programming mode, all the pins other than those that communicate in flash memory programming are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD0 or VSS0 via a resistor. When using the on-board clock, connect X1, X2, XT1, and XT2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main oscillator on-board, and leave the X2 pin open. The subsystem clock conforms to the normal operation mode. To use the power output from the flash programmer, connect the VDD0 and VDD1 pins to VDD of the flash programmer, and the VSS0 and VSS1 pins to GND of the flash programmer. To use the on-board power supply, make connections that accord with the normal operation mode. However, because the voltage is monitored by the flash programmer, be sure to connect VDD of the flash programmer. Supply the same power as in the normal operation mode to the other power supply pins (AVREF0, AVREF1, and AVSS).
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26.3.4 Connection of adapter for flash writing The following figures show examples of the recommended connection when the adapter for flash writing is used. Figure 26-10. Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-0)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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Figure 26-11. Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-1)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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Figure 26-12. Wiring Example for Flash Writing Adapter in 3-Wire Serial I/O Mode (SIO ch-2)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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Figure 26-13. Wiring Example for Flash Writing Adapter in UART Mode (UART ch-0)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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Figure 26-14. Wiring Example for Flash Writing Adapter in UART Mode (UART ch-1)
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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Figure 26-15. Wiring Example for Flash Writing Adapter in Pseudo 3-Wire Mode
VDD (2.7 to 5.5 V) GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 PD78F0058 50 11 PD78F0058Y 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND VDD VDD2 (LVDD)
SI
SO
SCK
CLKOUT RESET VPP RESERVE/HS WRITER INTERFACE
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CHAPTER 27 INSTRUCTION SET OVERVIEW
This chapter describes each instruction set of the PD780058 and 780058Y Subseries in table form. For details of the operations and operation codes, refer to the separate document 78K/0 Series Instructions User's Manual (U12326E).
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27.1 Conventions Used in Operation List
27.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: Absolute address specification * $: Relative address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 27-1. Operand Identifiers and Description Methods
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7), AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbol (16-bit manipulatable register even addresses only)Note FE20H to FF1FH Immediate data or label FE20H to FF1FH Immediate data or label (even address only) 0000H to FFFFH Immediate data or label (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or label 0040H to 007FH Immediate data or label (even address only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note
Addresses from FFD0H to FFDFH cannot be accessed with these operands. For special-function register symbols, see Table 5-2 Special-Function Register List.
Remark
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27.1.2 Description of operation column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( ): xH, xL: : : : ----: jdisp8: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value)
addr16: 16-bit immediate data or label
27.1.3 Description of flag operation column (Blank): Nt affected 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
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27.2 Operation List
Instruction Mnemonic Group 8-bit data transfer MOV Clocks Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A XCH A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3 Note 3 Note 3
Flag Operation r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A sfr A (DE) A (HL) x x x x x x Z AC CY
Bytes 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 1 2 2 3 1 1 2 2 2
Note 1
Note 2
4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8
- 7 7 - - 5 5 5 5 9+n 9+m 7 5 5 5+n 5+m 5+n 5+m 9+n 9+m 7+n 7+m 7+n 7+m - 6 6
10 + n + m A (addr16) 6+n+m 6+n+m
10 + n + m A (HL + byte) 10 + n + m A (HL + B) 10 + n + m A (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group 16-bit data transfer MOVW
Clocks Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX
Note 3 Note 3
Flag Operation Z AC CY rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX
Bytes 3 4 4 2 2 2 2 1 1 3 3
Note 3
Note 1
Note 2
6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 10 10 8 8 8 8 - -
12 + 2n AX (addr16) 12 + 2m (addr16) AX - - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XCHW 8-bit operation ADD
AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
1 2 3
Note 4
2 2 2 3 1 2 2 2 2 3
ADDC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 4
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE, or HL 4. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group 8-bit operation SUB
Clocks Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
Flag Operation Z AC CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY AA AA rr AA AA AA AA AA AA byte byte (saddr) (saddr) r A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Bytes 2 3 2 2 2 3 1 2 2 2 2 3
Note 3
Note 1
Note 2
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
SUBC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
AND
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from.
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Instruction Mnemonic Group 8-bit operation OR
Clocks Operands A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
Flag Operation Z AC CY A A byte (saddr) (saddr) byte AA r rr A A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) AA AA rr AA AA AA AA AA AA A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Bytes 2 3 2 2 2 3 1 2 2 2 2 3
Note 3
Note 1
Note 2
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
- 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n - 8 - - 5 9+n 5+n 9+n 9+n 9+n
XOR
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
2 2 2 3 1 2 2 2 2 3
CMP
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from.
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Instruction Mnemonic Group 16-bit operation ADDW SUBW CMPW Multiply/ divide MULU DIVUW
Clocks Operands AX, #word AX, #word AX, #word X C r saddr r saddr Bytes 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY 3 3 2 3 2 3 3 2 3 2
Note 1 Note 2
Flag Operation Z AC CY AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time (HL)3 - 0 (HL)7 - 4 x x x x x x x x x x x x x x x x x x x x x
6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10 4 4 6 - 4 - 6 6 - 4 - 6
- - - - - - 6 - 6 - - - - - -
Increment/ INC decrement DEC
INCW DECW Rotate ROR ROL RORC ROLC ROR4 ROL4 BCD adjust ADJBA ADJBS Bit manipulation MOV1
rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL]
12 + n + m A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, 12 + n + m A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0,
(HL)7 - 4 (HL)3 - 0 - - 7 7 - 7 7+n 8 8 - 8
8+n+m
Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY
x x
x x
x x x x x x x
x
x
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group Bit manipulation AND1
Clocks Operands CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit Bytes 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1
Note 1 Note 2
Flag Operation Z AC CY CY CY CY CY CY CY CY CY CY CY (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit x x x x x x x x x x x x x x x
6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2
7 7 - 7 7+n 7 7 - 7 7+n 7 7 - 7 7+n 6 8 - 6
OR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY CY CY CY CY CY CY CY CY sfr.bit 1 A.bit 1 PSW.bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 CY 1 CY 0 CY CY x x x x (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit
XOR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
(saddr.bit) 1
x
8 + n + m (HL).bit 1
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
6 8 - 6
x
8 + n + m (HL).bit 0
SET1 CLR1 NOT1
CY CY CY
- - -
1 0 x
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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Instruction Mnemonic Group Call/return CALL CALLF
Clocks Operands !addr16 !addr11 Bytes 3 2
Note 1 Note 2
Flag Operation Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 R R R R R R R R R
7 5
- -
CALLT
[addr5]
1
6
-
BRK
1
6
-
RET RETI
1 1
6 6
- -
RETB Stack manipulation PUSH PSW rp POP PSW rp MOVW SP, #word SP, AX AX, SP Unconditional branch BR !addr16 $addr16 AX Conditional BC branch BNC BZ BNZ $addr16 $addr16 $addr16 $addr16
1 1 1 1 1 4 2 2 3 2 2 2 2 2 2
6 2 4 2 4 - - - 6 6 8 6 6 6 6
- - - - - 10 8 8 - - - - - - -
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program.
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Instruction Mnemonic Group Conditional branch BT
Clocks Operands saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 Bytes 3 4 3 3 3 4 4 3 4 3 4
Note 1 Note 2
Flag Operation Z AC CY PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit then reset (HL).bit x x x
8 - 8 - 10 10 - 8 - 10 10
9 11 - 9 11 + n 11 11 - 11 11 + n 12
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
BTCLR
saddr.bit, $addr16
sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr, $addr16 CPU control SEL NOP EI DI HALT STOP RBn
4 3 4 3 2 2 3 2 1 2 2 2 2
- 8 - 10 6 6 8 4 2 - - 6 6
12 - 12
12 + n + m PC PC + 3 + jdisp8 if (HL).bit = 1
- - 10 - - 6 6 - -
B B - 1, then PC PC + 2 + jdisp8 if B 0 C C -1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or instruction that performs no data access is executed. 2. When an area except the internal high-speed RAM area is accessed Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 2. This clock cycle applies to the internal ROM program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to.
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27.3 Instructions Listed by Addressing Type
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
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Second Operand #byte First Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A rNote sfr saddr !addr16 PSW [DE] [HL]
[HL + byte] [HL + B] $addr16 [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
1 ROR ROL RORC ROLC
None
r
MOV
INC DEC
B, C sfr saddr MOV MOV
DBNZ
MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV MOV
DBNZ
INC DEC
!addr16 PSW
PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL + byte] [HL + B] [HL + C] X C
MOV
MULU DIVUW
Note
Except r = A
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(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand #word 1st Operand AX ADDW SUBW CMPW MOVW MOVWNote MOVW XCHW MOVW MOVW MOVW MOVW AX rp Note
sfrp
saddrp
!addr16
SP
None
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note
Only when rp = BC, DE, HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand
A.bit First Operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
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(4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand AX First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Compound instruction
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVREF0 AVREF1 AVSS Input voltage VI1 P00 to P05, P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 Output voltage Analog input voltage Output current, high VO VAN IOH P10 to P17 Per pin Total for P01 to P05, P30 to P37, P56, P57, P60 to P67, P120 to P127 Total for P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 Output current, low IOLNote Per pin for other than P50 to P57, P60 to P63 Per pin for P50 to P57, P60 to P63 Peak value rms value Peak value rms value Total for P50 to P55 Peak value rms value Total for P56, P57, P60 to P63 Peak value rms value Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Operating ambient temperature Storage temperature Tstg -65 to +150 C TA Peak value rms value Peak value rms value 20 15 30 10 100 70 100 70 50 20 50 20 -40 to +85 mA mA mA mA mA mA mA mA mA mA mA mA C -15 mA Analog input pin P60 to P63 N-ch open drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF0 + 0.3 -10 -15 V V V mA mA Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V
Note
The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
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Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Conditions VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V MIN. 1.0 TYP. MAX. 5.0 4 Unit MHz ms
X2
X1 IC
C2
C1
Crystal resonator
X2
X1 IC
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
5.0 10 30
MHz ms
C2
C1
External clock
X2
X1
X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH , tXL)
1.0 85
5.0 500
MHz ns
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V Conditions MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Unit kHz s
IC XT2 R2 C4
XT1
C3
External clock
XT2
XT1
XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
32
35
kHz
12
15
s
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 P60 to P63 MIN. TYP. MAX. 15 15 Unit pF pF
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Conditions P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, VDD = 1.8 to 5.5 V P120 to P127, P130, P131 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET VIH3 P60 to P63 (N-ch open drain) VIH4 X1, X2 VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VIH5 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 VNote Input voltage, low VIL1 P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, VDD = 1.8 to 5.5 V P120 to P127, P130, P131 VIL2 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET VIL3 P60 to P63 VDD = 1.8 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 V VIL4 X1, X2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VIL5 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 1.8 V VDD < 2.7 VNote Output voltage, high Output voltage, low VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 1.8 to 5.5 V, IOH = -100 A P50 to P57, P60 to P63 P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P70 to P72, P120 to P127, P130, P131 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 0.4 2.0 0.4 0.2VDD 0.15VDD 0.3VDD 0.2VDD 0.1VDD 0.4 0.2 0.2VDD 0.1VDD 0.1VDD V V V V V V V V V V V V V V MIN. 0.7VDD 0.8VDD 0.8VDD 0.85VDD 0.7VDD 0.8VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0.9VDD 0 0 TYP. MAX. VDD VDD VDD VDD 15 15 VDD VDD VDD VDD VDD 0.3VDD 0.2VDD Unit V V V V V V V V V V V V V
VIH2
VDD = 4.5 to 5.5 V, open drain, pulled-up (R = 1 k)
0.2VDD
V
VOL3
IOL = 400 A
0.5
V
Note Remark
When P07/XT1 pin is used as P07, the inverse phase of P07 should be input to XT2 pin using an inverter. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 VIN = 15 V VIN = 0 V P60 to P63 P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 P60 to P63 VIN = 0 V, P60 to P63 VIN = 0 V, P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 20 15 40 30 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 80 -3
A A A
ILIL2 ILIL3 Mask option pull-up resistor Software pull-up resistor R1 R2
-20 -3 Note 120 90
A A
k k
Note
When pull-up resistors are not connected to P60 to P63 (specified by the mask option), a low-level input leakage current of -200 A (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval, a -3 A (MAX.) current flows.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Output current, high Symbol IOH Per pin Total for all pins Output current, low IOL Per pin for P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 Per pin for P50 to P57, P60 to P63 Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Total for P50 to P57, P60 to P63 10 70 mA mA Conditions MIN. TYP. MAX. -1 -15 10 Unit mA mA mA
15 10
mA mA
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Power supply currentNote 5 Symbol IDD1 5.0 MHz crystal oscillation operating mode (fXX = 2.5 MHz)Note 3 5.0 MHz crystal oscillation operating mode (fXX = 5.0 MHz)Note 4 IDD2 5.0 MHz crystal oscillation HALT mode (fXX = 2.5 MHz)Note 3 Conditions VDD = 5.0 V 10%Note 1 10%Note 2 10%Note 1 10%Note 2 VDD = 3.0 V 10%Note 2 VDD = 2.0 V VDD = 5.0 V VDD = 3.0 V MIN. TYP. 3.5 0.92 0.47 6.1 1.6 MAX. 7.7 2.2 1.2 12.3 3.5 Unit mA mA mA mA mA
VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 2.0 V 10% Peripheral functions operating Peripheral functions not operating 0.19 1.1 0.46 mA mA 0.38 2.1 0.92 mA mA 0.97 5.5 2.4 mA mA
5.0 MHz crystal oscillation HALT mode (fXX = 5.0 MHz)Note 4
VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating 0.48 46 25 12.5 22.5 3.2 1.5 1.0 0.5 0.3 0.1 0.05 0.05 1.2 92 50 25 50 13.2 11.5 30 10 10 30 10 10 mA 3.3 mA 1.2 2.9 mA 7.5 mA
IDD3
32.768 kHz crystal oscillation operating modeNote 6
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
A A A A A A A A A A A A
IDD4
32.768 kHz crystal oscillation HALT modeNote 6
IDD5
XT1 = VDD STOP mode When feedback resistor is used XT1 = VDD STOP mode When feedback resistor is not used
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
IDD6
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
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Notes 1. High-speed mode operation (when the processor clock control register (PCC) is cleared to 00H). 2. Low-speed mode operation (when the PCC is set to 04H). 3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 4. Operation with main system clock fXX = fX (when OSMS is set to 01H) 5. Refer to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A converter, and on-chip pull-up resistor is not included. 6. When the main system clock operation is stopped.
AC Characteristics
(1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Minimum instruction execution time) Symbol TCY Conditions Operating with main system clock (fXX = 2.5 MHz)Note 1 Operating with main system clock (fXX = 5.0 MHz)Note 2 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V MIN. 0.8 2.0 0.4 0.8 40Note 3 2/fsam + 2/fsam + 0.1Note 4 0.2Note 4 122 TYP. MAX. 64 64 32 32 125 Unit
s s s s s s s s s s
Operating on subsystem clock TI00 input high-/ low-level width tTIH00 tTIL00 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 1.8 V VDD < 2.7 V TI01 input high-/ low-level width TI1, TI2 input frequency TI1, TI2 input high-/low-level width Interrupt request input high-/ low-level width INTP1 to INTP5, P40 to P47 tINTH tINTL INTP0 tTIH1 tTIL1 tTIH01 tTIL01 fTI1 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V
2/fsam + 0.5Note 4 10 20 0 0 100 1.8 4 275
MHz kHz ns
s s s s s s s s
3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 2.7 V VDD < 3.5 V 2/fsam + 1.8 V VDD < 2.7 V 2/fsam + VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V 0.2Note 4 0.5Note 4
10 20 10 20
RESET lowlevel width
tRSL
VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 2. Operation with main system clock fXX = fX (when OSMS is set to 01H) 3. Value when external clock is used. When a crystal resonator is used, it is 114 s (MIN.) 4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS) (when N = 0 to 4).
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TCY vs. VDD (@fXX = fX/2 main system clock operation)
TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
Cycle time TCY [s] Cycle time TCY [s]
10
Operation guaranteed range Operation guaranteed range
2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply voltage VDD [V]
0 1 2 3 4 5 6 Supply voltage VDD [V]
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(2) Read/write operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Time from address to data input Symbol tASTH tADS tADH tADD1 tADD2 Time from RD to data input tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Time from RD to WAIT input tRDWT1 tRDWT2 Time from WR to WAIT input WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Time from RD to address hold at external fetch Time from RD to write data output Time from WR to write data output Time from WR to address hold Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 40 0 0.85tCY 1.15tCY + 40 1.15tCY + 30 50 1.15tCY + 40 3.15tCY + 40 3.15tCY + 30 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 + 2n)tCY (2.85 + 2n)tCY - 100 20 (2.85 + 2n)tCY - 60 25 0.85tCY + 20 0.85tCY - 10 1.15tCY + 20 0 (2 + 2n)tCY - 60 (2.85 + 2n)tCY - 60 0.85tCY - 50 2tCY - 60 2tCY - 60 (2 + 2n)tCY Conditions MIN. 0.85tCY - 50 0.85tCY - 50 50 (2.85 + 2n)tCY - 80 (4 + 2n)tCY - 100 (2 + 2n)tCY - 100 (2.85 + 2n)tCY - 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.85tCY - 50
1.15tCY + 50
ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(b) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Time from address to data input Symbol tASTH tADS tADH tADD1 tADD2 Time from RD to data input tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Time from RD to WAIT input tRDWT1 tRDWT2 Time from WR to WAIT input WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Time from RD to address hold at external fetch Time from RD to write data output Time from WR to write data output Time from WR to address hold Delay time from WAIT to RD Delay time from WAIT to WR tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1 + 2n)tCY (2.4 + 2n)tCY - 60 20 (2.4 + 2n)tCY - 20 0.4tCY - 30 1.4tCY - 30 tCY - 10 tCY - 50 0.4tCY - 20 0 tCY 0.6tCY + 180 0.6tCY + 120 60 tCY + 60 2.6tCY + 180 2.6tCY + 120 tCY + 20 tCY + 50 0 (1.4 + 2n)tCY - 20 (2.4 + 2n)tCY - 20 tCY - 100 2tCY - 100 2tCY - 100 (2 + 2n)tCY Conditions MIN. tCY - 80 tCY - 80 0.4tCY - 10 (3 + 2n)tCY - 160 (4 + 2n)tCY - 200 (1.4 + 2n)tCY - 70 (2.4 + 2n)tCY - 70 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(c) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 1.8 to 2.7 V)
Parameter ASTB high-level width Address setup time Address hold time Time from address to data input Symbol tASTH tADS tADH tADD1 tADD2 Time from RD to data input tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 Time from RD to WAIT input tRDWT1 tRDWT2 Time from WR to WAIT input WAIT low-level width Write data setup time Write data hold time WR low-level width Delay time from ASTB to RD Delay time from ASTB to WR Delay time from RD to ASTB at external fetch Time from RD to address hold at external fetch Time from RD to write data output Time from WR to write data output Time from WR to address hold Delay time from WAIT to RD Delay time from WAIT to WR tRDWD tWRWD tWRADH tWTRD tWTWR 0.37tCY - 40 0 tCY 0.63tCY + 350 0.63tCY + 240 120 tCY + 120 2.63tCY + 350 2.63tCY + 240 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH (1 + 2n)tCY (2.37 + 2n)tCY - 100 20 (2.37 + 2n)tCY - 20 0.37tCY - 50 1.37tCY - 50 tCY - 10 tCY - 50 tCY + 20 tCY + 50 0 (1.37 + 2n)tCY - 20 (2.37 + 2n)tCY - 20 tCY - 200 2tCY - 200 2tCY - 200 (2 + 2n)tCY Conditions MIN. tCY - 150 tCY - 150 0.37tCY - 40 (3 + 2n)tCY - 320 (4 + 2n)tCY - 300 (1.37 + 2n)tCY - 120 (2.37 + 2n)tCY - 120 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(3) Serial interface (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK0 high-/low-level width SI0 setup time (to SCK0) tSIK1 tKH1, tKL1 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI0 hold time (from SCK0) Delay time from SCK0 to SO0 output
tKSI1
MIN. 800 1,600 3,200 4,800 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
tKSO1
C = 100 pFNote
300
ns
Note C is the load capacitance of the SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0 ... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK0 high-/low-level width tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI0 setup time (to SCK0) SI0 hold time (from SCK0) Delay time from SCK0 to SO0 output SCK0 rise/fall time tR2, tF2 tSIK2 2.0 V VDD 5.5 V 1.8 V VDD < 2.0 V tKSI2 C = 100 pFNote MIN. 800 1,600 3,200 4,800 400 800 1,600 2,400 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tKSO2
VDD = 2.0 to 5.5V VDD = 1.8 to 5.5V
300 500 160
ns ns ns
When using external device expansion function When not using external device expansion function
1,000
ns
Note C is the load capacitance of the SO0 output line.
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(iii) 2-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 R = 1 k, C = 100 pFNote Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK0 high-level width tKH3 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCK0 low-level width tKL3 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SB0, SB1 hold time (from SCK0) Delay time from SCK0 to SB0, SB1 output tKSI3 MIN. 1,600 3,200 4,800 tKCY3/2 - 160 tKCY3/2 - 190 tKCY3/2 - 50 tKCY3/2 - 100 300 350 400 500 600 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tKSO3 0 300 ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) 2-wire serial I/O mode (SCK0 ... Internal clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK0 high-level width tKH4 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK0 low-level width tKL4 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) Delay time from SCK0 to SB0, SB1 output tKSI4 tSIK4 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V MIN. 1,600 3,200 4,800 650 1,300 2,100 800 1,600 2,400 100 150 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
tKSO4
R = 1 k, C = 100 pFNote
4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V
0 0 0
300 500 800 160
ns ns ns ns
SCK0 rise/fall time
tR4, tF4
When using external device expansion function When not using external device expansion function
1,000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(v) SBI mode (SCK0 ... Internal clock output) (PD78005x only)
Parameter SCK0 cycle time Symbol tKCY5 Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) tKH5, tKL5 4.5 V VDD 5.5 V 1.8 V VDD < 4.5 V tSIK5 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V SB0, SB1 hold time (from SCK0) Delay time from SCK0 to SB0, SB1 output SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSI5 tKSO5 R = 1 k, C = 100 tKSB tSBK tSBH tSBL pFNote VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V MIN. 800 3,200 4,800 tKCY5/2 - 50 tKCY5/2 - 150 100 300 400 tKCY5/2 0 0 tKCY5 tKCY5 tKCY5 tKCY5 250 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) SBI mode (SCK0 ... External clock input) (PD78005x only)
Parameter Symbol tKCY6 Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V MIN. 800 3,200 4,800 400 1,600 2,400 100 300 400 tKCY6/2 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 0 0 tKCY6 tKCY6 tKCY6 tKCY6 When using external device expansion function When not using external device expansion function 160 1,000 300 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SCK0 cycle time
SCK0 high-/low-level width
tKH6, tKL6
SB0, SB1 setup time (to SCK0)
tSIK6
SB0, SB1 hold time (from SCK0) Delay time from SCK0 to SB0, SB1 output SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise/fall time
tKSI6 tKSO6
tKSB tSBK tSBH tSBL tR6, tF6
Note
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(vii) I2C bus mode (SCL ... Internal clock output) (PD78005xY only)
Parameter SCL cycle time Symbol tKCY7 R = 1 K, C = 100 pFNote Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCL high-level width tKH7 VDD = 2.7 to 5.5 V VDD = 1.8 to 5.5 V SCL low-level width tKL7 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V SDA0, SDA1 setup time (to SCL) tSIK7 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SDA0, SDA1 hold time (from SCL) Delay time from SCL to SDA0, SDA1 output tKSI7 tKSO7 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 tKSB tSBK VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V SDA0, SDA1 high-level width tSBH MIN. 10 20 30 tKCY7 - 160 tKCY7 - 190 tKCY7 - 50 tKCY7 - 100 200 300 400 0 0 0 0 200 400 500 500 300 500 600 TYP. MAX. Unit
s s s
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL ... External clock input) (PD78005xY only)
Parameter Symbol tKCY8 tKH8, tKL8 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V tKSI8 tKSO8 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 1.8 V VDD < 2.0 V 0 0 0 0 200 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V 400 500 500 800 160 1 300 500 600 Conditions MIN. 1,000 400 600 200 300 ns ns ns ns ns ns ns ns ns ns TYP. MAX. Unit ns ns ns ns ns
SCL cycle time SCL high-/low-level width
SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) Delay time from SCL to SDA0, SDA1 output
tSIK8
SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1
tKSB tSBK
SDA0, SDA1 high-level width
tSBH
VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V
SCL rise/fall time
tR8, tF8
When using external device expansion function When not using external device expansion function
s
Note
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
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(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK1 high/low-level width tKH9, tKL9 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output tKSI9 tKSO9 C = 100 pFNote MIN. 800 1,600 3,200 4,800 tKCY9/2 - 50 tKCY9/2 - 100 100 150 300 400 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines. (ii) 3-wire serial I/O mode (SCK1 ... External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK1 high/low-level width tKH10,tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI1 setup time (to SCK1) tSIK10 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output SCK1 rise/fall time tKIS10 tKSO10 C = 100 pFNote VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V tR10, tF10 When using external device expansion function When not using external device expansion function MIN. 800 1,600 3,200 4,800 400 800 1,600 2,400 100 150 400 300 500 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SO1 output line.
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(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK1 high-/low-level width tKH11,tKL11 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output STB from SCK1 Strobe signal high-level width tKSI11 tKSO11 tSBD tSBW 2.7 V VDD < 5.5 V 2.0 V < VDD < 2.7 V 1.8 V VDD < 2.0 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK1 from busy inactive tSPS 100 150 200 300 2tKCY11 ns ns ns ns ns tBYS C = 100 pFNote tKCY11/2 - 100 tKCY11 - 30 tKCY11 - 60 tKCY11 - 90 100 MIN. 800 1,600 3,200 4,800 tKCY11/2 - 50 tKCY11/2 - 100 100 150 300 400 400 300 tKCY11/2 + 100 tKCY11 + 30 tKCY11 + 60 tKCY11 + 90 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines.
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(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter SCK1 cycle time Symbol tKCY12 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK1 high-/low-level width tKH12, tKL12 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI1 setup time (to SCK1) tSIK12 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V SI1 hold time (from SCK1) Delay time from SCK1 to SO1 output SCK1 rise/fall time tR12, tF12 tKSI12 tKSO12 C = 100 pFNote VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V When using external device expansion function When not using external device expansion function MIN. 800 1,600 3,200 4,800 400 800 1,600 2,400 100 150 400 300 500 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SO1 output line.
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(c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2...Internal clock output)
Parameter SCK2 cycle time Symbol tKCY13 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK2 high-/low-level width tKH13, tKL13 tSIK13 VDD = 4.5 to 5.5 V VDD = 1.8 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI2 hold time (from SCK2) Delay time from SCK2 to SO2 output tKSI13 tKSO13 C = 100 pFNote MIN. 800 1,600 3,200 4,800 tKCY13/2 - 50 tKCY13/2 - 100 100 150 300 400 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2)
Note C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter SCK2 cycle time Symbol tKCY14 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SCK2 high-/low-level width tKH14, tKL14 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V SI2 setup time (to SCK2) tSIK14 VDD = 2.0 to 5.5 V VDD = 1.8 to 5.5 V SI2 hold time (from SCK2) Delay time from SCK2 to SO2 output SCK2 rise/fall time tKSI14 tKSO14 C = 100 pFNote VDD = 2.0 to 5.5 V VDD = 2.0 to 5.5 V tR14, tF14 Other than below VDD = 4.5 to 5.5 V When not using external device expansion function MIN. 800 1,600 3,200 4,800 400 800 1,600 2,400 100 150 400 300 500 160 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
s
Note C is the load capacitance of the SO2 output line.
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(iii) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V MIN. TYP. MAX. 78,125 39,063 19,531 9,766 Unit bps bps bps bps
(iv) UART mode (external clock input)
Parameter ASCK cycle time Symbol tKCY15 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V ASCK high-/low-level width tKH15, tKL15 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V Transfer rate 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 1.8 V VDD < 2.0 V ASCK rise/fall time tR15, VDD = 4.5 to 5.5 V, when not using external device expansion function. Other than above 160 ns MIN. 800 1,600 3,200 4,800 400 800 1,600 2,400 39,063 19,531 9,766 6,510 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns bps bps bps bps ns
tF15
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AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Point of measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2
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Interrupt Request Input Timing
tINTL INTP0 to INTP5, P40 to P47
tINTH
RESET Input Timing
tRSL
RESET
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Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z
Operation code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1 AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z tRDD1
Operation code tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
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External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
RD tASTRD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
tASTRD RD tRDL2 tRDWD tWDWR WR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
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Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tRn SCK0 to SCK2 tSIKm tKSIm tKHm tFn
SI0 to SI2 tKSOm
Input data
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4 tR4 SCK0 tSIK3, 4 tKSO3, 4 SB0, SB1
tKH3, 4 tF4
tKSI3, 4
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SBI mode (bus release signal transfer):
tKCY5, 6 tKL5, 6 tR6 SCK0 tKSB tSBL tSBH tSBK tSIK5, 6 tKSI5, 6 tKH5, 6 tF6
SB0, SB1 tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6 tR6 SCK0
tKH5, 6
tF6
tSIK5, 6 tKSB tSBK tKSI5, 6
SB0, SB1 tKSO5, 6
I2C bus mode:
tF8
tR8
tKCYm
SCL tKLm tKHm tKSOm SDA0, SDA1 tSIKm tKSB tSBK tKSB
tKSIm
tSBH
m = 7, 8
tSIKm
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3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12
tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1
tR12
tKL11, 12
tSBD
tSBW
STB
tKCY11, 12
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note tBYS
10 + nNote tBYH tSPS
1
BUSY (Active high)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
tKCY15 t KL15 tR15 tKH15 tF15
ASCK
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A/D Converter Characteristics (PD780053, 780053(A), 780054, 780054(A), 780055, 780055(A), 780056, 780056(A), 780058B, 780058B(A), 780053Y, 780053Y(A), 780054Y, 780054Y(A), 780055Y, 780055Y(A), 780056Y, 780056Y(A), 780058BY, 780058BY(A)) (TA = -40 to +85C, VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 1.8 V AVREF0 < 2.7 V 2.7 V AVREF0 5.5 V Conversion time TCONV1 TCONV2 Analog input voltage Reference voltage AVREF0 current VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 operatingNote 3 1.8 V AVREF0 < 2.7 V 2.7 V AVREF0 5.5 V 40 16 AVSS 1.8 500 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.4 0.6 100 100 AVREF0 VDD 1,500 3 Unit bit %FSR %FSR
s s
V V
A A
When A/D converter is not
Notes 1. Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR). 2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
A/D Converter Characteristics (PD780058) (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 TCONV VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 16 AVSS 2.7 500 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.6 100 AVREF0 VDD 1,500 3 Unit bit %FSR
Conversion time Analog input voltage Reference voltage AVREF0 current
s
V V
A A
When A/D converter is not operatingNote 3
Notes 1. Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR). 2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0. Caution The operating voltage range of the A/D converter and D/A converter of the PD780058 is VDD = 2.7 to 5.5 V.
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D/A Converter Characteristics (PD780053, 780053(A), 780054, 780054(A), 780055, 780055(A), 780056, 780056(A), 780058B, 780058B(A), 780053Y, 780053Y(A), 780054Y, 780054Y(A), 780055Y, 780055Y(A), 780056Y, 780056Y(A), 780058BY, 780058BY(A)) (TA = -40 to +85C, VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R=2 R=4 MNote 1 MNote 1
Note 1
Symbol
Conditions
MIN.
TYP.
MAX. 8 1.2 0.8 0.6 10 15
Unit bit % % %
R = 10 MNote 1 Settling time C = 30 pF AVREF1 = 1.8 to 2.7 V AVREF1 = 1.8 to 5.5 V Output resistance Analog reference voltage AVREF1 current RO AVREF1 IREF1 Note 2 DACS0, DACS1 = 55HNote 2 4 8 Note 2 1.8 8
s s
k
VDD 2.5
V mA k
Resistance between AVREF1 and AVSS RAIREF1
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1
D/A Converter Characteristics (PD780058) (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R=2 R=4 MNote 1 MNote 1
Note 1
Symbol
Conditions
MIN.
TYP.
MAX. 8 1.2 0.8 0.6 15
Unit bit % % %
R = 10 MNote 1 Settling time Output resistance Analog reference voltage AVREF1 current RO AVREF1 IREF1 Note 2 DACS0, DACS1 = 55HNote 2 4 8 C = 30 pF Note 2 2.7
s
k
8 VDD 2.5
V mA k
Resistance between AVREF1 and AVSS RAIREF1
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel Remark DACS0 and DACS1: D/A conversion value setting registers 0, 1 Caution The operating voltage range of the A/D converter and D/A converter of the PD780058 is VDD = 2.7 to 5.5 V.
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Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
10
A
Release signal set time Oscillation stabilization wait time
tSREL tWAIT
s
2 /fX Note
17
ms ms
Note
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency
Remark
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
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Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVREF0 AVREF1 AVSS Input voltage VI1 P00 to P05, P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 Output voltage Analog input voltage Output current, high VO VAN IOH P10 to P17 Per pin Total for P01 to P05, P30 to P37, P56, P57, P60 to P67, P120 to P127 Total for P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 Output current, low IOLNote 2 Per pin for other than P50 to P57, P60 to P63 Per pin for P50 to P57, P60 to P63 Peak value rms value Peak value rms value Total for P50 to P55 Peak value rms value Total for P56, P57, P60 to P63 Peak value rms value Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Operating ambient temperature Storage temperature Tstg TA During normal operation During flash memory programming Peak value rms value Peak value rms value 20 10 30 15 100 70 100 70 50 20 50 20 -40 to +85 10 to 40 -65 to +125 mA mA mA mA mA mA mA mA mA mA mA mA C C C -15 mA Analog input pin P60 to P63 N-ch open drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF0 + 0.3 -10 -15 V V V mA mA Note 1 Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V V
(The Note is described on the next page.) Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
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Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. - When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (see a in the figure below). - When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below).
VDD
2.7 V 0V a b
VPP 2.7 V 0V
2. The rms value should be calculated as follows: [rms value] = [Peak value] x Duty
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Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Conditions VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V MIN. 1.0 TYP. MAX. 5.0 4 Unit MHz ms
X2
X1 VPP
C2
C1
Crystal resonator
X2
X1 VPP
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
5.0 10 30
MHz ms
C2
C1
External clock
X2
X1
X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH , tXL)
1.0 85
5.0 500
MHz ns
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V Conditions MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Unit kHz s
VPP XT2 R2 C4
XT1
C3
External clock
XT2
XT1
XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
32
35
kHz
12
15
s
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 P60 to P63 MIN. TYP. MAX. 15 15 Unit pF pF
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input voltage, Symbol VIH1 high Conditions P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, P50 to P57, P64-P67, P71, P120 to P127, P130, P131 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET VIH3 P60 to P63 (N-ch open drain) VIH4 VIH5 X1, X2 XT1/P07, XT2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Input voltage, low VIL1 P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 VIL2 VIL3 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET P60 to P63 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VIL4 VIL5 X1, X2 XT1/P07, XT2 VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Output voltage, high Output voltage, low P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P70 to P72, P120-P127, P130, P131 VOL2 SB0, SB1, SCK0 VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 2.7 to 5.5 V, IOH = -100 A P50 to P57, P60 to P63 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 0.4 2.0 0.4 0.2VDD 0.3VDD 0.2VDD 0.4 0.2VDD 0.1VDD V V V V V V V V V V VDD - 0.5 0.8 VDD 0.9 VDD 0 VDD VDD VDD 0.3 VDD V V V V VDD = 2.7 to 5.5 V 0.7 VDD 15 V MIN. 0.7 VDD TYP. MAX. VDD Unit V
VIH2
0.8 VDD
VDD
V
VDD = 4.5 to 5.5 V, open drain, pulled-up (R = 1 k)
0.2 VDD
V
VOL3
IOL = 400 A
0.5
V
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 VIN = 15 V VIN = 0 V P60 to P63 P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 P60-P63 VIN = 0 V, P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 30 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 80 -3
A A A
ILIL2 ILIL3 Software pull-up resistor R
-20 -3 Note 90
A A
k
Note
A low-level input leakage current of -200 A (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval, a -3 A (MAX.) current flows.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Output current, high Symbol IOH Per pin Total for all pins Output current, low IOL Per pin for P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 Per pin for P50 to P57, P60 to P63 Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Total for P50 to P57, P60 to P63 10 mA Conditions MIN. TYP. MAX. -1 -15 10 Unit mA mA mA
15 10
mA mA
70
mA
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Power supply current Symbol IDD1Note 5 5.0 MHz crystal oscillation operating mode (fXX = 2.5 MHz)Note 3 5.0 MHz crystal oscillation operating mode (fXX = 5.0 MHz)Note 4 5.0 MHz crystal oscillation HALT mode (fXX = 2.5 MHz)Note 3 Conditions VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating 5.0 MHz crystal oscillation HALT mode (fXX = 5.0 MHz)Note 4 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating IDD3Note 5 32.768 kHz crystal oscillation operating modeNote 6 IDD4Note 5 32.768 kHz crystal oscillation HALT modeNote 6 IDD5Note 5 XT1 = VDD STOP mode When feedback resistor is used VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% 110 86 22.5 3.2 1.0 0.5 0.1 0.05 220 172 50 13.2 30 10 30 10 0.6 4.5 1.5 mA mA 1.3 8.4 3.1 mA mA 0.44 1.1 mA 2.9 mA 1.0 5.6 2.8 mA mA MIN. TYP. 6.2 1.3 13.1 2.1 MAX. 12.5 3.1 25.7 4.9 Unit mA mA mA mA
IDD2
A A A A A A A A
IDD6Note 5 XT1 = VDD STOP mode When feedback resistor is not used
Notes 1. High-speed mode operation (when the processor clock control register (PCC) is cleared to 00H). 2. Low-speed mode operation (when PCC is set to 04H). 3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 4. Operation with main system clock fXX = fX (when OSMS is set to 01H) 5. Refers to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A converter, and on-chip pull-up resistor is not included. 6. When the main system clock operation is stopped.
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AC Characteristics
(1) Basic operation (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Conditions Operating with main system clock (fXX = 2.5 MHz)Note 1 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 0.4 0.8 40Note 3 2/fsam + 2/fsam + 0.1Note 4 0.2Note 4 122 32 32 125 VDD = 2.7 to 5.5 V MIN. 0.8 TYP. MAX. 64 Unit
s s s s s s s
Operating with main system clock (fXX = 5.0 MHz)Note 2
Operating with subsystem clock TI00 input high-/ low-level width TI01 input high-/ low-level width TI1, TI2 input frequency TI1, TI2 input high-/low-level width Interrupt request input high-/ low-level width RESET lowlevel width tRSL tINTH tINTL INTP1 to INTP5, P40 to P47 VDD = 2.7 to 5.5 V INTP0 tTIH1 tTIL1 tTIH00 tTIL00 tTIH01 tTIL01 fTI1 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V VDD = 2.7 to 5.5 V
10
0 0 100 1.8
4 275
MHz kHz ns
s s s s s
3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 2.7 V VDD < 3.5 V 2/fsam + VDD = 2.7 to 5.5 V 0.2Note 4
10 10
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 2. Operation with main system clock fXX = fX (when OSMS is set to 01H) 3. Value when external clock is used. When a crystal resonator is used, it is 114 s (MIN.) 4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS) (when N = 0 to 4).
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TCY vs. VDD (@fXX = fX/2 main system clock operation)
TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
10
Cycle time TCY [s]
2.0 1.0 0.5 0.4
Cycle time TCY [s]
Guaranteed operation range
Operation guaranteed range
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply voltage VDD [V]
0 1 2 3 4 5 6 Supply voltage VDD [V]
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(2) Read/write operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 0 0.85tCY 1.15tCY + 40 1.15tCY + 30 50 1.15tCY + 40 3.15tCY + 40 3.15tCY + 30 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 + 2n)tCY (2.85 + 2n)tCY - 100 20 (2.85 + 2n)tCY - 60 25 0.85tCY + 20 0.85tCY - 10 1.15tCY + 20 0 (2 + 2n)tCY - 60 (2.85 + 2n)tCY - 60 0.85tCY - 50 2tCY - 60 2tCY - 60 (2 + 2n)tCY Conditions MIN. 0.85tCY - 50 0.85tCY - 50 50 (2.85 + 2n)tCY - 80 (4 + 2n)tCY - 100 (2 + 2n)tCY - 100 (2.85 + 2n)tCY - 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.85tCY - 50
1.15tCY + 50
ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(b) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1 + 2n)tCY (2.4 + 2n)tCY - 60 20 (2.4 + 2n)tCY - 20 0.4tCY - 30 1.4tCY - 30 tCY - 10 tCY - 50 0.4tCY - 20 0 tCY 0.6tCY + 180 0.6tCY + 120 60 tCY + 60 2.6tCY + 180 2.6tCY + 120 tCY + 20 tCY + 50 0 (1.4 + 2n)tCY - 20 (2.4 + 2n)tCY - 20 tCY - 100 2tCY - 100 2tCY - 100 (2 + 2n)tCY Conditions MIN. tCY - 80 tCY - 80 0.4tCY - 10 (3 + 2n)tCY - 160 (4 + 2n)tCY - 200 (1.4 + 2n)tCY - 70 (2.4 + 2n)tCY - 70 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(3) Serial interface (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 tSIK1 tKH1, tKL1 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI1 MIN. 800 1,600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSO1
C = 100 pFNote
300
ns
Note C is the load capacitance of the SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0 ... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise/fall time tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK2 2.7 V VDD 5.5 V MIN. 800 1,600 400 800 100 TYP. MAX. Unit ns ns ns ns ns
tKSI2 C = 100 pFNote
400
ns
tKSO2
300
ns
tR2, tF2
When using external device expansion function When not using external device expansion function
160 1,000
ns ns
Note C is the load capacitance of the SO0 output line.
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(iii) 2-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY3 tKH3 tKL3 R = 1 k, C = 100 pFNote Conditions 2.7 V VDD 5.5 V VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tSIK3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI3 tKSO3 MIN. 1,600 tKCY3/2 - 160 tKCY3/2 - 50 tKCY3/2 - 100 300 350 600 0 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) 2-wire serial I/O mode (SCK0 ... External clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise/fall time Symbol tKCY4 tKH4 tKL4 tSIK4 tKSI4 R = 1 k, C = 100 tR4, tF4 pFNote 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Conditions 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V VDD = 2.7 to 5.5 V MIN. 1,600 650 800 100 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns
tKSO4
0 0
300 500 160
ns ns ns
When using external device expansion function When not using external device expansion function
1,000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(v) SBI mode (SCK0 ... Internal clock output) (PD78F0058 only)
Parameter SCK0 cycle time Symbol tKCY5 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKH5, tKL5 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK5 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI5 tKSO5 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V MIN. 800 3,200 tKCY5/2 - 50 tKCY5/2 - 150 100 300 tKCY5/2 0 0 tKCY5 tKCY5 tKCY5 tKCY5 250 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSB tSBK tSBH tSBL
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) SBI mode (SCK0 ... External clock input) (PD78F0058 only)
Parameter SCK0 cycle time Symbol tKCY6 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise/fall time tKH6, tKL6 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSIK6 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tKSI6 tKSO6 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V MIN. 800 3,200 400 1,600 100 300 tKCY6/2 0 0 tKCY6 tKCY6 tKCY6 tKCY6 When using external device expansion function When not using external device expansion function 160 1,000 300 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSB tSBK tSBH tSBL tR6, tF6
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(vii) I2C bus mode (SCL ... Internal clock output) (PD78F0058Y only)
Parameter SCL cycle time SCL high-level width SCL low-level width Symbol tKCY7 tKH7 tKL7 R = 1 k, Conditions 2.7 V VDD < 5.5 V 4.5 V VDD < 5.5 V 2.7 V VDD < 4.5 V SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tKSO7 tKSB tSBK tSBH 4.5 V VDD < 5.5 V 2.7 V VDD < 4.5 V 0 0 200 400 500 300 500 ns ns ns ns ns tSIK7 2.7 V VDD < 5.5 V MIN. 10 tKCY7 - 160 tKCY7 - 50 tKCY7 - 100 200 TYP. MAX. Unit
s s
ns ns ns
C = 100 pFNote 2.7 V VDD < 5.5 V
tKSI7
0
ns
Note
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL ... External clock input) (PD78F0058Y only)
Parameter Symbol tKCY8 tKH8 tSIK8 Conditions MIN. 1 400 200 TYP. MAX. Unit
SCL cycle time SCL high-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width
s
ns ns
tKSI8
0
ns
tKSO8
R = 1 k,
4.5 V VDD < 5.5 V
0 0 200
300 500
ns ns ns
C = 100 pFNote 2.7 V VDD < 4.5 V tKSB
tSBK tSBH
400 500
ns ns
Note
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
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(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH9, tKL9 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSI9 tKSO9 C = 100 pFNote MIN. 800 1,600 tKCY9/2 - 50 tKCY9/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1 ... External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH10, tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time from SCK1 SCK1 rise/fall time tSIK10 tKIS10 tKSO10 tR10, tF10 C = 100 pFNote VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
When using external device expansion function When not using external device expansion function
Note C is the load capacitance of the SO1 output line.
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(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH11, tKL11 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time from SCK1 STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tKSI11 tKSO11 tSBD tSBW tBYS tBYH 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V tSPS 2.7 V VDD < 5.5 V C = 100 pFNote tKCY11/2 - 100 tKCY11 - 30 100 100 150 2tKCY11 MIN. 800 1,600 tKCY11/2 - 50 tKCY11/2 - 100 100 150 400 300 tKCY11/2 + 100 tKCY11 + 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... External clock input)
Parameter SCK1 cycle time Symbol tKCY12 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK1 high-/low-level width tKH12, tKL12 tSIK12 tKSI12 tKSO12 tR12, tF12 C = 100 pFNote VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time from SCK1 SCK1 rise/fall time
When using external device expansion function When not using external device expansion function
Note C is the load capacitance of the SO1 output line.
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(c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2 ... Internal clock output)
Parameter SCK2 cycle time Symbol tKCY13 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK2 high-/low-level width tKH13, tKL13 tSIK13 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI13 tKSO13 C = 100 pFNote MIN. 800 1,600 tKCY13/2 - 50 tKCY13/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2)
Note C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2 ... External clock input)
Parameter SCK2 cycle time Symbol tKCY14 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V SCK2 high-/low-level width tKH14, tKL14 tSIK14 tKSI14 tKSO14 tR14, tF14 C = 100 pFNote VDD = 2.7 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 2.7 to 5.5 V MIN. 800 1,600 400 800 100 400 300 160 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise/fall time
Other than below VDD = 4.5 to 5.5 V When not using external device expansion function
s
Note C is the load capacitance of the SO2 output line.
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(iii) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V MIN. TYP. MAX. 78,125 39,063 Unit bps bps
(iv) UART mode (external clock input)
Parameter ASCK cycle time Symbol tKCY15 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK high-/low-level width tKH15, tKL15 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Transfer rate 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V ASCK rise/fall time tR15, tF15 VDD = 4.5 to 5.5 V, when not using external device expansion function. Other than above 160 ns MIN. 800 1,600 400 800 39,063 19,531 1,000 TYP. MAX. Unit ns ns ns ns bps bps ns
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AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Point of measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2
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Interrupt Request Input Timing
tINTL INTP0 to INTP5, P40 to P47
tINTH
RESET Input Timing
tRSL
RESET
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Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z
Operation code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1 AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z tRDD1
Operation code tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
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External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
RD tASTRD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
tASTRD RD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
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Serial Transfer Timing
3-wire serial I/O mode:
tKCYm tKLm tRn SCK0 to SCK2 tSIKm tKSIm tKHm tFn
SI0 to SI2 tKSOm
Input data
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4 tR4 SCK0 tSIK3, 4 tKSO3, 4 SB0, SB1
tKH3, 4 tF4
tKSI3, 4
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SBI mode (bus release signal transfer):
tKCY5, 6 tKL5, 6 tR6 SCK0 tKSB tSBL tSBH tSBK tSIK5, 6 tKSI5, 6 tKH5, 6 tF6
SB0, SB1 tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6 tR6 SCK0
tKH5, 6
tF6
tSIK5, 6 tKSB tSBK tKSI5, 6
SB0, SB1 tKSO5, 6
I2C bus mode:
tKCYm
SCL tKLm tKHm tKSOm SDA0, SDA1 tSIKm tKSB tSBK tKSB
tKSIm
tSBH m = 7, 8
tSIKm
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3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12
tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1
tR12
tKL11, 12
tSBD
tSBW
STB
tKCY11, 12
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note tBYS
10 + nNote tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
tKCY15 t KL15 tR15 tKH15 tF15
ASCK
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A/D Converter Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 2.7 V AVREF0 < 4.5 V 4.5 V AVREF0 5.5 V Conversion time Analog input voltage Reference voltage AVREF0 current TCONV VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 2.7 V AVREF0 5.5 V 16 AVSS 2.7 500 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.0 0.6 100 AVREF0 VDD 1,500 3 Unit bit %FSR %FSR
s
V V
A A
When A/D converter is not operatingNote 3
Notes 1. Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR). 2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
D/A Converter Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R=2 MNote 1 Symbol Conditions MIN. TYP. MAX. 8 1.2 0.8 0.6 15 8 1.8 Note 2 DACS0, DACS1 = 55HNote 2 4 8 VDD 2.5 Unit bit % % %
R = 4 MNote 1 R = 10 Settling time Output resistance Analog reference voltage AVREF1 current Resistance between AVREF1 and AVSS RO AVREF1 IREF1 RAIREF1 MNote 1
Note 1
C = 30 pF Note 2
s
k V mA k
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel Remark DACS0 and DACS1: D/A conversion value set registers 0, 1
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Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
10
A
Release signal set time Oscillation stabilization wait time
tSREL tWAIT
s
2 /fX Note
17
ms ms
Note
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency
Remark
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
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Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, TA = 10 to 40C)
(1) Write/delete characteristics
Parameter Write current (VDD pin)Note 1 Symbol IDDW When VPP = VPP1 Conditions 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Write current (VPP pin)Note 1 IPPW When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Delete current (VDD pin)Note 1 IDDE When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Delete current (VPP pin)Note 1 Unit delete time Total delete time Number of overwrite VPP power supply voltage IPPE tER tERA CWRT VPP0 VPP1 Delete and write are counted as one cycle In normal mode At flash memory programming 0 9.7 10.0 When VPP = VPP1 0.5 1 MIN. TYP. MAX. 15.5 Unit mA
28.7
mA
19.5
mA
32.7
mA
15.5
mA
28.7
mA
100 1 20 20 0.2 VDD 10.3
mA s s times V V
Notes 1. AVREF current and Port current (current flowing to internal pull-up resistor) are not included. 2. When main system clock is operating at fXX = fXX/2 (when oscillation mode select register (OSMS) is cleared to 00H). 3. When main system clock is operating at fXX = fXX (when OSMS is set to 01H). 2) Serial write operation characteristics
Parameter VPP setup time VPP setup time from VDD RESET setup time from VPP VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 VPP high voltage VPP high voltage VPP high voltage Conditions MIN. 1.0 10 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
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Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPP VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
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Caution The product that can operate on VDD = 2.2 V has "0232" or later as the first 4 digits of the lot number inscribed on the package.
If this number is "0232" or later, VDD = 2.2 V Lot number Year Week code code Rank
Internal control code
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD VPP AVREF0 AVREF1 AVSS Input voltage VI1 P00 to P05, P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 Output voltage Analog input voltage VO VAN P10 to P17 Analog input pin P60 to P63 N-ch open drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF0 + 0.3 V V V Note Conditions Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V V
Note
Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (2.2 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.2 V) of the operating voltage range of VDD (see b in the figure below).
VDD
2.2 V 0V a b
VPP 2.2 V 0V
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Absolute Maximum Ratings (TA = 25C)
Parameter Output current, high Symbol IOH Per pin Total for P01 to P05, P30 to P37, P56, P57, P60 to P67, P120 to P127 Total for P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 Output current, low IOLNote Per pin for other than P50 to P57, P60 to P63 Per pin for P50 to P57, P60 to P63 Peak value rms value Peak value rms value Total for P50 to P55 Peak value rms value Total for P56, P57, P60 to P63 Peak value rms value Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Operating ambient temperature Storage temperature Tstg TA During normal operation During flash memory programming Peak value rms value Peak value rms value 20 10 30 15 100 70 100 70 50 20 50 20 -40 to +85 10 to 40 -65 to +125 mA mA mA mA mA mA mA mA mA mA mA mA C C C -15 mA Conditions Ratings -10 -15 Unit mA mA
Note
The rms value should be calculated as follows: [rms value] = [Peak value] x Duty Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Caution
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Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit Parameter Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 Conditions VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V MIN. 1.0 TYP. MAX. 5.0 4 Unit MHz ms
X2
X1 VPP
C2
C1
Crystal resonator
X2
X1 VPP
Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2
5.0 10 30
MHz ms
C2
C1
External clock
X2
X1
X1 input frequency (fX)Note 1 X1 input high-/low-level width (tXH , tXL)
1.0 85
5.0 500
MHz ns
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Resonator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V Conditions MIN. 32 TYP. 32.768 1.2 MAX. 35 2 10 Unit kHz s
VPP XT2 R2 C4
XT1
C3
External clock
XT2
XT1
XT1 input frequency (fXT)Note 1 XT1 input high-/low-level width (tXTH , tXTL)
32
35
kHz
12
15
s
Notes 1. Indicates only oscillator characteristics. See AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. f = 1 MHz Unmeasured pins returned to 0 V. P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 P60 to P63 MIN. TYP. MAX. 15 15 Unit pF pF
20
pF
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Conditions P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, VDD = 2.2 to 5.5 V P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET VIH3 P60 to P63 (N-ch open drain) VIH4 X1, X2 VDD = 2.2 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VIH5 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V Input voltage, low VIL1 P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, VDD = 2.2 to 5.5 V P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 P00 to P05, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V P33, P34, P70, P72, RESET VDD = 2.2 to 5.5 V P60 to P63 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V VIL4 VIL5 X1, X2 XT1/P07, XT2 VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V Output voltage, high Output voltage, low VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 2.2 to 5.5 V, IOH = -100 A P50 to P57, P60 to P63 P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P70 to P72, P120-P127, P130, P131 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA MIN. 0.7 VDD 0.8 VDD TYP. MAX. VDD VDD Unit V V
VIH2
0.8 VDD 0.85 VDD 0.7 VDD 0.8 VDD VDD - 0.5 VDD - 0.2 0.8 VDD 0.9 VDD 0.9 VDD 0 0
VDD VDD 15 15 VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD
V V V V V V V V V V V
VIL2 VIL3
0 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 0.4
0.2 VDD 0.15 VDD 0.3 VDD 0.2 VDD 0.1 VDD 0.4 0.2 0.2 VDD 0.1 VDD 0.1 VDD
V V V V V V V V V V V V
2.0 0.4
V V
VDD = 4.5 to 5.5 V, open drain, pulled-up (R = 1 k)
0.2VDD
V
VOL3
IOL = 400 A
0.5
V
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 VIN = 15 V VIN = 0 V P60 to P63 P00 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET X1, X2, XT1/P07, XT2 P60-P63 VIN = 0 V, P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 30 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 80 -3
A A A
ILIL2 ILIL3 Software pull-up resistor R
-20 -3 Note 90
A A
k
Note
A low-level input leakage current of -200 A (MAX.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval, a -3 A (MAX.) current flows.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter Output current, high Symbol IOH Per pin Total for all pins Output current, low IOL Per pin for P01 to P05, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 Per pin for P50 to P57, P60 to P63 Total for P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 Total for P01 to P05, P30 to P37, P64 to P67, P120 to P127 Total for P50 to P57. P60 to P63 10 mA Conditions MIN. TYP. MAX. -1 -15 10 Unit mA mA mA
15 10
mA mA
70
mA
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter Power supply current Symbol IDD1Note 5 5.0 MHz crystal oscillation operating mode (fXX = 2.5 MHz)Note 3 5.0 MHz crystal oscillation operating mode (fXX = 5.0 MHz)Note 4 IDD2 5.0 MHz crystal oscillation HALT mode (fXX = 2.5 MHz)Note 3 Conditions VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 2.2 VNote 2 VDD = 5.0 V 10%Note 1 VDD = 3.0 V 10%Note 2 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 2.2 V Peripheral functions operating Peripheral functions not operating 5.0 MHz crystal oscillation HALT mode (fXX = 5.0 MHz)Note 4 VDD = 5.0 V 10% Peripheral functions operating Peripheral functions not operating VDD = 3.0 V 10% Peripheral functions operating Peripheral functions not operating IDD3Note 5 32.768 kHz crystal oscillation operating modeNote 6 IDD4Note 5 32.768 kHz crystal oscillation HALT modeNote 6 IDD5Note 5 XT1 = VDD STOP mode When feedback resistor is used IDD6Note 5 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V VDD = 5.0 V 10% 0.6 110 86 70 22.5 3.2 1.5 1.0 0.5 0.3 0.1 0.05 0.05 4.5 1.5 220 172 140 56 13.2 11.5 30 10 10 30 10 10 mA mA 1.3 8.4 3.1 mA mA 0.25 1.5 0.6 mA mA 0.44 2.9 1.1 mA mA 1.0 5.6 2.8 mA mA MIN. TYP. 6.2 1.3 0.68 13.1 2.1 MAX. 12.5 3.1 1.6 25.7 4.9 Unit mA mA mA mA mA
A A A A A A A A A A A A
XT1 = VDD STOP mode VDD = 3.0 V 10% When feedback resistor is not used VDD = 2.2 V
Notes 1. High-speed mode operation (when the processor clock control register (PCC) is cleared to 00H). 2. Low-speed mode operation (when PCC is set to 04H). 3. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 4. Operation with main system clock fXX = fX (when OSMS is set to 01H) 5. Refers to the current flowing to the VDD0 and VDD1 pins. The current flowing to the A/D converter, D/A converter, and on-chip pull-up resistor is not included. 6. When the main system clock operation is stopped.
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AC Characteristics
(1) Basic operation (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Conditions Operating with main system clock (fXX = 2.5 MHz)Note 1 VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V MIN. 0.8 2.0 0.4 0.8 40Note 3 2/fsam + 2/fsam + 0.1Note 4 0.2Note 4 122 TYP. MAX. 64 64 32 32 125 Unit
s s s s s s s s s s
Operating with main system clock (fXX = 5.0 MHz)Note 2
Operating with subsystem clock TI00 input high-/ low-level width tTIH00 tTIL00 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 2.2 V VDD < 2.7 V TI01 input high-/ low-level width TI1, TI2 input frequency TI1, TI2 input high-/low-level width Interrupt request input high-/ low-level width INTP1 to INTP5, P40 to P47 tINTH tINTL INTP0 tTIH1 tTIL1 tTIH01 tTIL01 fTI1 VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V
2/fsam + 0.5Note 4 10 20 0 0 100 1.8 4 275
MHz kHz ns
s s s s s s s s
3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 2.7 V VDD < 3.5 V 2/fsam + 2.2 V VDD < 2.7 V 2/fsam + VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V 0.2Note 4 0.5Note 4
10 20 10 20
RESET lowlevel width
tRSL
VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V
Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode select register (OSMS) is cleared to 00H) 2. Operation with main system clock fXX = fX (when OSMS is set to 01H) 3. Value when external clock is used. When a crystal resonator is used, it is 114 s (MIN.) 4. Selection of fsam = fXX/2N, fXX/32, fXX/64, and fXX/128 is possible with bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS) (when N = 0 to 4).
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TCY vs. VDD (@fXX = fX/2 main system clock operation)
TCY vs. VDD (@fXX = fX main system clock operation)
60
60
10
10
Cycle time TCY [s]
Cycle time TCY [s]
Guaranteed operation range
Operation guaranteed range
2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply voltage VDD [V]
0 1 2 3 4 5 6 Supply voltage VDD [V]
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(2) Read/write operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 0 0.85tCY 1.15tCY + 40 1.15tCY + 30 50 1.15tCY + 40 3.15tCY + 40 3.15tCY + 30 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 + 2n)tCY (2.85 + 2n)tCY - 100 20 (2.85 + 2n)tCY - 60 25 0.85tCY + 20 0.85tCY - 10 1.15tCY + 20 0 (2 + 2n)tCY - 60 (2.85 + 2n)tCY - 60 0.85tCY - 50 2tCY - 60 2tCY - 60 (2 + 2n)tCY Conditions MIN. 0.85tCY - 50 0.85tCY - 50 50 (2.85 + 2n)tCY - 80 (4 + 2n)tCY - 100 (2 + 2n)tCY - 100 (2.85 + 2n)tCY - 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.85tCY - 50
1.15tCY + 50
ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(b) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 2.7 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1 + 2n)tCY (2.4 + 2n)tCY - 60 20 (2.4 + 2n)tCY - 20 0.4tCY - 30 1.4tCY - 30 tCY - 10 tCY - 50 0.4tCY - 20 0 tCY 0.6tCY + 180 0.6tCY + 120 60 tCY + 60 2.6tCY + 180 2.6tCY + 120 tCY + 20 tCY + 50 0 (1.4 + 2n)tCY - 20 (2.4 + 2n)tCY - 20 tCY - 100 2tCY - 100 2tCY - 100 (2 + 2n)tCY Conditions MIN. tCY - 80 tCY - 80 0.4tCY - 10 (3 + 2n)tCY - 160 (4 + 2n)tCY - 200 (1.4 + 2n)tCY - 70 (2.4 + 2n)tCY - 70 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(c) When MCS = 0 or PCC2 to PCC0 000B (TA = -40 to +85C, VDD = 2.2 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD at external fetch Address hold time from RD at external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR tCY - 50 0.37tCY - 40 0 tCY 0.63tCY + 350 0.63tCY + 240 120 tCY + 120 2.63tCY + 350 2.63tCY + 240 tCY + 50 ns ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1 + 2n)tCY (2.37 + 2n)tCY - 100 20 (2.37 + 2n)tCY - 20 0.37tCY - 50 1.37tCY - 50 tCY - 10 tCY + 20 0 (1.37 + 2n)tCY - 20 (2.37 + 2n)tCY - 20 tCY - 200 2tCY - 200 2tCY - 200 (2 + 2n)tCY Conditions MIN. tCY - 150 tCY - 150 0.37tCY - 40 (3 + 2n)tCY - 320 (4 + 2n)tCY - 300 (1.37 + 2n)tCY - 120 (2.37 + 2n)tCY - 120 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Bit 0 of the oscillation mode select register (OSMS) PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC) tCY = TCY/4 n indicates the number of waits.
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(3) Serial interface (TA = -40 to +85C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK0 high-/low-level width SI0 setup time (to SCK0) tSIK1 tKH1, tKL1 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSO1 C = 100 pFNote 300 ns tKSI1 MIN. 800 1,600 3,200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0 ... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK0 high-/low-level width tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise/fall time tSIK2 MIN. 800 1,600 3,200 400 800 1,600 100 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSI2 C = 100 pFNote
400
ns
tKSO2
300
ns
tR2, tF2
When using external device expansion function When not using external device expansion function
160 1,000
ns ns
Note C is the load capacitance of the SO0 output line.
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(iii) 2-wire serial I/O mode (SCK0 ... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 R = 1 k, C = 100 SCK0 high-level width tKH3 pFNote Conditions 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V SCK0 low-level width tKL3 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSO3 0 300 ns tKSI3 MIN. 1,600 3,200 tKCY3/2 - 160 tKCY3/2 - 190 tKCY3/2 - 50 tKCY3/2 - 100 300 350 400 600 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) 2-wire serial I/O mode (SCK0 ... External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V SCK0 high-level width tKH4 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V SCK0 low-level width tKL4 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise/fall time tSIK4 tKSI4 R = 1 k, C = 100 tR4, tF4 pFNote 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V MIN. 1,600 3,200 650 1,300 800 1,600 100 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns ns ns
tKSO4
0 0
300 500 160
ns ns ns
When using external device expansion function When not using external device expansion function
1,000
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(v) SBI mode (SCK0 ... Internal clock output) (PD78F0058, 78F0058Y only)
Parameter SCK0 cycle time Symbol tKCY5 Conditions 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKH5, tKL5 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V tSIK5 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V tKSI5 tKSO5 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V MIN. 800 3,200 tKCY5/2 - 50 tKCY5/2 - 150 100 300 tKCY5/2 0 0 tKCY5 tKCY5 tKCY5 tKCY5 250 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSB tSBK tSBH tSBL
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) SBI mode (SCK0 ... External clock input) (PD78F0058, 78F0058Y only)
Parameter SCK0 cycle time Symbol tKCY6 Conditions 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise/fall time tKH6, tKL6 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V tSIK6 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V tKSI6 tKSO6 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V MIN. 800 3,200 400 1,600 100 300 tKCY6/2 0 0 tKCY6 tKCY6 tKCY6 tKCY6 When using external device expansion function When not using external device expansion function 160 1,000 300 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKSB tSBK tSBH tSBL tR6, tF6
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
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(vii) I2C bus mode (SCL ... Internal clock output) (PD78F0058Y only)
Parameter SCL cycle time Symbol tKCY7 R = 1 k, Conditions 2.7 V VDD 5.5 V MIN. 10 20 tKCY7 - 160 tKCY7 - 190 tKCY7 - 50 tKCY7 - 100 200 300 0 TYP. MAX. Unit
s
ns ns ns ns ns ns ns ns
C = 100 pFNote 2.2 V VDD < 2.7 V SCL high-level width tKH7 VDD = 2.7 to 5.5 V VDD = 2.2 to 5.5 V SCL low-level width tKL7 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tSBK tSBH tKSB tKSO7 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V tSIK7 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V tKSI7
0 0 200 400 500
300 500
ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL ... External clock input) (PD78F0058Y only)
Parameter Symbol tKCY8 tKH8 tSIK8 Conditions MIN. 1 400 200 TYP. MAX. Unit
SCL cycle time SCL high-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width
s
ns ns
tKSI8 4.5 V VDD 5.5 V 2.2 V VDD < 4.5 V
0
ns
tKSO8
R = 1 k, C = 100 pFNote
0 0 200
300 500
ns ns ns
tKSB
tSBK tSBH
400 500
ns ns
Note
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
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(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK1 high-/low-level width tKH9, tKL9 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSI9 tKSO9 C = 100 pFNote MIN. 800 1,600 3,200 tKCY9/2 - 50 tKCY9/2 - 100 100 150 300 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1 ... External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK1 high-/low-level width tKH10, tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time from SCK1 SCK1 rise/fall time tSIK10 tKIS10 tKSO10 tR10, tF10 C = 100 pFNote MIN. 800 1,600 3,200 400 800 1,600 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
When using external device expansion function When not using external device expansion function
Note C is the load capacitance of the SO1 output line.
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(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... Internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK1 high-/low-level width tKH11, tKL11 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI1 hold time (from SCK1) SO1 output delay time from SCK1 STB from SCK1 Strobe signal high-level width tKSI11 tKSO11 tSBD tSBW 2.7 V VDD < 5.5 V 2.2 V VDD < 2.7 V Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYS tBYH 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK1 from busy inactive tSPS C = 100 pFNote tKCY11/2 - 100 tKCY11 - 30 tKCY11 - 60 100 100 150 200 2tKCY11 MIN. 800 1,600 3,200 tKCY11/2 - 50 tKCY11/2 - 100 100 150 300 400 300 tKCY11/2 + 100 tKCY11 + 30 tKCY11 + 60 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SCK1 and SO1 output lines. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... External clock input)
Parameter SCK1 cycle time Symbol tKCY12 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK1 high-/low-level width tKH12, tKL12 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time from SCK1 SCK1 rise/fall time tSIK12 tKSI12 tKSO12 tR12, tF12 C = 100 pFNote When using external device expansion function When not using external device expansion function MIN. 800 1,600 3,200 400 800 1,600 100 400 300 160 1,000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
Note C is the load capacitance of the SO1 output line.
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(c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2 ... Internal clock output)
Parameter SCK2 cycle time Symbol tKCY13 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK2 high-/low-level width tKH13, tKL13 tSIK13 VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI13 tKSO13 C = 100 pFNote MIN. 800 1,600 3,200 tKCY13/2 - 50 tKCY13/2 - 100 100 150 300 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
SI2 setup time (to SCK2)
Note C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2 ... External clock input)
Parameter SCK2 cycle time Symbol tKCY14 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SCK2 high-/low-level width tKH14, tKL14 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise/fall time tSIK14 tKSI14 tKSO14 tR14, tF14 C = 100 pFNote MIN. 800 1,600 3,200 400 800 1,600 100 400 300 160 1 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Other than below VDD = 4.5 to 5.5 V When not using external device expansion function
s
Note C is the load capacitance of the SO2 output line.
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(iii) UART mode (dedicated baud rate generator output)
Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V MIN. TYP. MAX. 78,125 39,063 19,531 Unit bps bps bps
(iv) UART mode (external clock input)
Parameter ASCK cycle time Symbol tKCY15 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V ASCK high-/low-level width tKH15, tKL15 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V Transfer rate 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.2 V VDD < 2.7 V ASCK rise/fall time tR15, tF15 VDD = 4.5 to 5.5 V, when not using external device expansion function. Other than above 160 ns MIN. 800 1,600 3,200 400 800 1,600 39,063 19,531 9,766 1,000 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps ns
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AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD 0.2VDD
Point of measurement
0.8VDD 0.2VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 input
1/fXT
tXTL XT1 input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1, TI2
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Interrupt Request Input Timing
tINTL INTP0 to INTP5, P40 to P47
tINTH
RESET Input Timing
tRSL
RESET
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Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address tADD1
AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z
Operation code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1 AD0 to AD7 tADS tASTH ASTB
Lower 8-bit address
Hi-Z tRDD1
Operation code tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
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External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
RD tASTRD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWDS tWDH tWRADH
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2 AD0 to AD7 tADS tADH tASTH ASTB
Lower 8-bit address
Hi-Z tRDD2
Read data
Hi-Z
Write data
Hi-Z
tRDH
tASTRD RD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
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Serial Transfer Timing
3-wire serial I/O mode:
tKCYm tKLm tRn SCK0 to SCK2 tSIKm tKSIm tKHm tFn
SI0 to SI2 tKSOm
Input data
SO0 to SO2
Output data
m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14
2-wire serial I/O mode:
tKCY3, 4
tKL3, 4 tR4 SCK0 tSIK3, 4 tKSO3, 4 SB0, SB1
tKH3, 4 tF4
tKSI3, 4
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SBI mode (bus release signal transfer):
tKCY5, 6 tKL5, 6 tR6 SCK0 tKSB tSBL tSBH tSBK tSIK5, 6 tKSI5, 6 tKH5, 6 tF6
SB0, SB1 tKSO5, 6
SBI mode (command signal transfer):
tKCY5,6
tKL5, 6 tR6 SCK0
tKH5, 6
tF6
tSIK5, 6 tKSB tSBK tKSI5, 6
SB0, SB1 tKSO5, 6
I2C bus mode:
tKCYm
SCL tKLm tKHm tKSOm SDA0, SDA1 tSIKm tKSB tSBK tKSB
tKSIm
tSBH m = 7, 8
tSIKm
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3-wire serial I/O mode with automatic transmit/receive function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12
tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1
tR12
tKL11, 12
tSBD
tSBW
STB
tKCY11, 12
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9Note
10Note tBYS
10 + nNote tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
UART mode (external clock input):
tKCY15 t KL15 tR15 tKH15 tF15
ASCK
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A/D Converter Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote 1 2.7 V AVREF0 5.5 V 2.2 V AVREF0 < 2.7 V Conversion time TCONV1 TCONV2 Analog input voltage Reference voltage AVREF0 current VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 When A/D converter is not operatingNote 3 2.2 V AVREF0 < 2.7 V 2.7 V AVREF0 < 5.5 V 40 16 AVSS 2.2 500 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.6 1.4 100 100 AVREF0 VDD 1,500 3.0 Unit bit %FSR %FSR
s s
V V
A A
Notes 1. Excludes quantization error (1/2 LSB). This value is indicated as a ratio to the full-scale value (%FSR). 2. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to the AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 0.
D/A Converter Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R=2 MNote 1 Symbol Conditions MIN. TYP. MAX. 8 1.2 0.8 0.6 AVREF1 = 2.2 to 2.7 V AVREF1 = 2.2 to 5.5 V Output resistance Analog reference voltage AVREF1 current Resistance between AVREF1 and AVSS RO AVREF1 IREF1 RAIREF1 Note 2 DACS0, DACS1 = 55HNote 2 4 8 Note 2 1.8 8 VDD 2.5 10 15 Unit bit % % %
R = 4 MNote 1 R = 10 MNote 1 Overall errorNote 1 C= 30 pFNote 1
s s
k V mA k
Notes 1. R and C are the D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel Remark DACS0 and DACS1: D/A conversion value set registers 0, 1
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Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET Release by interrupt request
0.1
10
A
Release signal set time Oscillation stabilization wait time
tSREL tWAIT
s
2 /fX Note
17
ms ms
Note
Selection of 212/fXX and 214/fXX to 217/fXX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency
Remark
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode STOP mode Operating mode
Data retention mode
VDD STOP instruction execution Standby release signal (Interrupt request)
VDDDR tSREL
tWAIT
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ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V))
Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, TA = 10 to 40C)
(1) Write/erase characteristics
Parameter Write current (VDD pin)Note 1 Symbol IDDW When VPP = VPP1 Conditions 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Write current (VPP pin)Note 1 IPPW When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Erase current (VDD pin)Note 1 IDDE When VPP = VPP1 5.0 MHz crystal oscillation operation mode (fXX = 2.5 MHz)Note 2 5.0 MHz crystal oscillation operation mode (fXX = 5.0 MHz)Note 3 Erase current (VPP pin)Note 1 Unit erase time Total erase time Number of overwrites VPP power supply voltage IPPE tER tERA CWRT VPP0 VPP1 Erase and write are counted as one cycle In normal mode During flash memory programming 0 9.7 10.0 When VPP = VPP1 0.5 1 MIN. TYP. MAX. 15.5 Unit mA
28.7
mA
19.5
mA
32.7
mA
15.5
mA
28.7
mA
100 1 20 20 0.2 VDD 10.3
mA s s times V V
Notes 1. AVREF current and port current (current flowing to internal pull-up resistors) are not included. 2. When main system clock is operating at fXX = fXX/2 (when oscillation mode select register (OSMS) is cleared to 00H). 3. When main system clock is operating at fXX = fXX (when OSMS is set to 01H). 2) Serial write operation characteristics
Parameter VPP setup time VPP setup time from VDD RESET setup time from VPP VPP count start time from RESET Count execution time VPP counter high-level width VPP counter low-level width VPP counter noise elimination width Symbol tPSRON tDRPSR tPSRRF tRFCF tCOUNT tCH tCL tNFW 8.0 8.0 40 VPP high voltage VPP high voltage VPP high voltage Conditions MIN. 1.0 10 1.0 1.0 2.0 TYP. MAX. Unit
s s s s
ms
s s
ns
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ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V))
Flash Write Mode Setting Timing
VDD VDD 0V VPPH VPP VPP VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V tCL tDRPSR tRFCF tCH
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CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES)
VDD vs IDD (mask ROM version, fX = 5.0 MHz, fXX = 2.5 MHz)
(TA = 25C) 10
PCC = 00H PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillating, XT1 oscillating)
1
Supply current IDD [mA]
0.1
PCC = B0H
HALT (X1 stopped, XT1 oscillating)
0.01
0.001 0 2 3 4 5 6 7
Supply voltage VDD [V]
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CHARACTERISTICS CURVES (REFERENCE VALUES)
VDD vs IDD (mask ROM version, fX = fXX = 5.0 MHz)
(TA = 25C) 10
PCC = 00H PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillating, XT1 oscillating)
Approximately the same curve
1
Supply current IDD [mA]
0.1
PCC = B0H
HALT (X1 stopped, XT1 oscillating)
0.01
0.001 0 2 3 4 5 6 7
Supply voltage VDD [V]
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CHAPTER 32 PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 +7 3 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
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PACKAGE DRAWINGS
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D Q R
80 1 20
21
F G H P I
M
J
K S N S
L M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.1450.05 0.10 1.00.05 0.10.05 3 +7 -3 1.2 MAX. S80GK-50-9EU-1
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CHAPTER 33
RECOMMENDED SOLDERING CONDITIONS
The PD780058 and 780058Y Subseries should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Table 33-1. Surface Mounting Type Soldering Conditions (1/4) (1) PD780053GC-xxx-8BT: 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14) 80-pin plastic QFP (14 x 14)
PD780054GC-xxx-8BT: PD780055GC-xxx-8BT: PD780056GC-xxx-8BT: PD780058GC-xxx-8BT: PD780058BGC-xxx-8BT: PD780053YGC-xxx-8BT: PD780054YGC-xxx-8BT: PD780055YGC-xxx-8BT: PD780056YGC-xxx-8BT: PD780058BYGC-xxx-8BT: PD780053GC(A)-xxx-8BT: PD780054GC(A)-xxx-8BT: PD780055GC(A)-xxx-8BT: PD780056GC(A)-xxx-8BT: PD780058BGC(A)-xxx-8BT: PD780053YGC(A)-xxx-8BT: PD780054YGC(A)-xxx-8BT: PD780055YGC(A)-xxx-8BT: PD780056YGC(A)-xxx-8BT:
PD780058BYGC(A)-xxx-8BT: 80-pin plastic QFP (14 x 14)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less Wave soldering Soldering bath temperature: 260C or less, Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C or less, Time: 3 seconds max. (per pin row) - WS60-00-1 VP15-00-2 Soldering Conditions Recommended Condition Symbol IR35-00-2
Caution
Do not use different soldering methods together (except for partial heating).
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RECOMMENDED SOLDERING CONDITIONS
Table 33-1. Surface Mounting Type Soldering Conditions (2/4) (2) PD78F0058GC-8BT: 80-pin plastic QFP (14 x 14)
PD78F0058YGC-8BT: 80-pin plastic QFP (14 x 14)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 days VPS
Note
Soldering Conditions
Recommended Condition Symbol IR35-107-2
(after that, prebake at 125C for 10 hours) VP15-107-2
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 days
Note
(after that, prebake at 125C for 10 hours) WS60-107-1
Wave soldering
Soldering bath temperature: 260C or less, Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Exposure limit: 7 days
Note
(after that, prebake at 125C for 10 hours) -
Partial heating
Pin temperature: 300C or less, Time: 3 seconds max. (per pin row)
Note
After opening the dry pack, store it below 25C and 65% RH for the allowable storage period. Do not use different soldering methods together (except for partial heating).
Caution
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CHAPTER 33
RECOMMENDED SOLDERING CONDITIONS
Table 33-1. Surface Mounting Type Soldering Conditions (3/4) (3) PD780053GK-xxx-9EU: 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12) 80-pin plastic TQFP (12 x 12)
PD780054GK-xxx-9EU: PD780055GK-xxx-9EU: PD780056GK-xxx-9EU: PD780058GK-xxx-9EU: PD780058BGK-xxx-9EU: PD780053YGK-xxx-9EU: PD780054YGK-xxx-9EU: PD780055YGK-xxx-9EU: PD780056YGK-xxx-9EU:
PD780058BYGK-xxx-9EU: 80-pin plastic TQFP (12 x 12)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 days VPS
Note
Soldering Conditions
Recommended Condition Symbol IR35-107-2
(after that, prebake at 125C for 10 hours) VP15-107-2
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 days
Note
(after that, prebake at 125C for 10 hours) - - -
Wave soldering Partial heating
Pin temperature: 300C or less, Time: 3 seconds max. (per pin row)
Note
After opening the dry pack, store it below 25C and 65% RH for the allowable storage period. Do not use different soldering methods together (except for partial heating).
Caution
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RECOMMENDED SOLDERING CONDITIONS
Table 33-1. Surface Mounting Type Soldering Conditions (4/4) (4) PD78F0058GK-9EU: 80-pin plastic TQFP (12 x 12)
PD78F0058YGK-9EU: 80-pin plastic TQFP (12 x 12)
Soldering Method Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 3 days VPS
Note
Soldering Conditions
Recommended Condition Symbol IR35-103-2
(after that, prebake at 125C for 10 hours) VP15-103-2
Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 3 days
Note
(after that, prebake at 125C for 10 hours) - - -
Wave soldering Partial heating
Pin temperature: 300C or less, Time: 3 seconds max. (per pin row)
Note
After opening the dry pack, store it below 25C and 65% RH for the allowable storage period. Do not use different soldering methods together (except for partial heating).
Caution
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APPENDIX A DIFFERENCES BETWEEN PD78054, 78058F, AND 780058 SUBSERIES
Table A-1 shows the major differences between the PD78054, 78058F, and 780058 Subseries. Table A-1. Major Differences Between PD78054, 78058F, and 780058 Subseries (1/2)
Product Name Item EMI noise measures Supply voltage PROM version Flash memory version Internal ROM size None VDD = 2.0 to 6.0 V Provided VDD = 2.7 to 6.0 V Provided VDD = 1.8 to 5.5 VNote None
PD78054 Subseries
PD78058F Subseries
PD780058 Subseries
PD78P054, 78P058
None
PD78P058F
None
PD78F0058 PD780053: PD780054: PD780055: PD780056: PD780058B: PD780058: PD78F0058:
1,024 bytes 24 32 40 48 60 60 60 KB KB KB KB KB KB KB
PD78052: PD78053: PD78054: PD78P054: PD78056: PD78058: PD78P058:
16 24 32 32 48 60 60
KB KB KB KB KB KB KB
PD78056F: 48 KB PD78058F: 60 KB PD78P058F: 60 KB
Internal high-speed RAM size
PD78052: 512 bytes PD78053, 78054, 78P054, 78056, 78058, 78P058: 1,024 bytes
Total: * CMOS input: * CMOS I/O: * N-ch open-drain I/O: Power supply for A/D converter
1,024 bytes
I/O ports
69 pins 2 pins 63 pins 4 pins Power supply for A/D converter and port output buffer
Total: * CMOS input: * CMOS I/O:
68 pins 2 pins 62 pins
* N-ch open-drain I/O: 4 pins None (power supplied to port output buffer is VDD0)
AVDD pin
AVREF0 pin
Reference voltage input to A/D converter
Reference voltage input and analog power supply to A/D converter - The results of the first A/D conversion immediately after the A/D conversion operation has started (CS set to 1) may not satisfy the ratings; therefore take appropriate measures such as discarding the results. 3-wire serial I/O/UART mode with time division function 6 sources NP-80GC, NP-80GK, EP-78230GC-R, EP-78054GK-R DF780058
Caution on operation immediately after A/D conversion starts
-
Serial interface channel 2
3-wire serial I/O/UART mode
External maskable interrupts Emulation probe
7 sources EP-78230GC-R, EP-78054GK-R
Device file
DF78054
Note
VDD of flash memory version (PD78F0058) = 2.7 to 5.5 V
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DIFFERENCES BETWEEN PD78054, 78058F, AND 780058 SUBSERIES
Table A-1. Major Differences Between PD78054, 78058F, and 780058 Subseries (2/2)
Product Name Item Package * 80-pin plastic QFP * 80-pin plastic QFP (14 x 14) (14 x 14) * 80-pin plastic QFP * 80-pin plastic QFP (14 x 14) (14 x 14) * 80-pin ceramic WQFN * 80-pin plastic TQFP (14 x 14) (Fine pitch) (12 x 12) (PD78P054, 78P058 only) (PD78058F only) Refer to data sheet of individual product. * 80-pin plastic QFP (14 x 14) * 80-pin plastic TQFP (Fine pitch) (12 x 12)
PD78054 Subseries
PD78058F Subseries
PD780058 Subseries
Electrical specifications and recommended soldering conditions
See CHAPTERS 28 to 30 ELECTRICAL SPECIFICATIONS and CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS.
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APPENDIX B
DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the PD780058, 780058Y Subseries. Figure B-1 shows a configuration example of the tools.
*
Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatible machines can be used for PC98NX series computers. When using PC98-NX series computers, refer to the description for IBM PC/AT compatible machines.
*
Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95 * Windows 98 * Windows 2000 * Windows NTTM Ver. 4.0
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DEVELOPMENT TOOLS
Figure B-1. Configuration of Development Tools
Software package * Software package
Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1
Debugging software * Integrated debugger * System simulator
Control software * Project Manager (Windows only)Note 2 Embedded software * Real-time OS
Host machine (PC or EWS) Interface adapter, PC card interface, etc.
Power supply unit
Flash memory write environment Flash programmer
In-circuit emulator Emulation board
Flash memory write adapter
I/O board
Flash memory
Performance board
Emulation probe
Conversion socket or conversion adapter Target system
Notes 1. The C library source file is not included in the software package. 2. The Project Manager is included in the assembler package. The Project Manager is only used for Windows.
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APPENDIX B
DEVELOPMENT TOOLS
B.1 Software Package
SP78K0 Software package This package contains various software tools for 78K/0 Series development. The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: SxxxxSP78K0
Remark xxxx in the part number differs depending on the OS used.
SxxxxSP78K0
xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM
B.2 Language Processing Software
RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780058) (sold separately). This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) in Windows. Part Number: SxxxxRA78K0 CC78K0 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an assembler package and device file (both sold separately). This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) in Windows. Part Number: SxxxxCC78K0 DF780058Note 1 Device file This file contains information peculiar to the device. This device file should be used in combination with tools (RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and RX78K0) (sold separately). The corresponding OS and host machine differ depending on the tool used. Part Number: SxxxxDF780058 CC78K0-LNote 2 C library source file This is a source file of functions configuring the object library included in the C compiler package. This file is required to match the object library included in C compiler package to the user's specifications. It does not depend on the operating environment because it is a source file. Part Number: SxxxxCC78K0-L
Notes 1. The DF780058 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and RX78K0. 2. CC78K0-L is not included in the software package (SP78K0).
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DEVELOPMENT TOOLS
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxRA78K0 SxxxxCC78K0
xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700TM Host Machine PC-9800 series, IBM PC/AT and compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UXTM (Rel. 10.10) SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.1) CD-ROM Supply Medium 3.5-inch 2HD FD
SPARCstationTM
SxxxxDF780058 SxxxxCC78K0-L
xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT and compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD
B.3 Control Software
Project Manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the Project Manager. The Project Manager is included in the assembler package (RA78K0). It can only be used in Windows.
B.4 Flash Memory Writing Tools
Flashpro III (Part number: FL-PR3, PG-FP3) Flashpro IV (Part number: FL-PR4, PG-FP4) Flash programmer FA-80GC-8BT FA-80GK-9EU Flash memory writing adapter Flash programmer dedicated to microcontrollers with on-chip flash memory.
Flash memory writing adapter used connected to Flashpro III/Flashpro IV. * FA-80GC-8BT: 80-pin plastic QFP (GC-8BT type) * FA-80GK-9EU: 80-pin plastic TQFP (GK-9EU type)
Remark FL-PR3, FL-PR4, FA-80GC-8EU, and FA-80GK-9EU are products of Naito Densei Machida Mfg. Co., Ltd. Contact: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
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APPENDIX B
DEVELOPMENT TOOLS
B.5 Debugging Tools (Hardware)
B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A
IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It corresponds to an integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. This board is used for extending the IE-78K0-NS functions, and is used connected to the IE-78K0-NS. With the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. In-circuit emulator that combines the IE-78K0-NS and IE-78K0-NS-PA This adapter is used for supplying power from a 100 to 240 V AC output.
IE-78K0-NS-PA Performance board
IE-78K0-NS-A In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-780308-NS-EM1 Emulation board
This adapter is required when using a PC-9800 series computer (except notebook type) as the IE-78K0-NS host machine (C bus compatible). This is PC card and interface cable required when using a notebook-type computer as the IE-78K0-NS host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC/AT compatible computer as the IE-78K0NS host machine (ISA bus compatible). This adapter is required when using a PC with a PCI bus as the IE-78K0-NS host machine. This board emulates the operations of the peripheral hardware peculiar to a device (common to PD780308 subseries). It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator to the target system and is designed for an 80-pin plastic QFP (GC-8BT type). It should be used in combination with the TGC080SBP.
NP-80GC-TQ NP-H80GC-TQ Emulation probe TGC-080SBP Conversion adapter (See Figure B-2) NP-80GC Emulation Probe EV-9200GC-80 Conversion Socket (See Figure B-2) NP-80GK Emulation Probe TGK-080SDW Conversion Adapter (See Figure B-3)
This conversion socket connects the NP-80GC-TQ or NP-H80GC-TQ to the target system board designed to mount an 80-pin plastic QFP (GC-8BT type).
This probe is for an 80-pin plastic QFP (GC-8BT type) and connects an in-circuit emulator and the target system. This conversion socket connects the board of the target system created to mount an 80-pin plastic QFP (GC-8BT type) and NP-80GC.
This probe is for an 80-pin plastic TQFP (GK-9EU type) and connects an in-circuit emulator and the target system. This conversion adapter connects the board of the target system created to mount 80-pin plastic TQFP (GK-9EU type) and TGK-080SDW.
Remarks 1. NP-80GC, NP-80GC-TQ, NP-H80GC-TQ, and NP-80GK are products of Naito Densei Machida Mfg. Co., Ltd. Contact: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. 2. TGC-080SBP and TGK-080SDW are products of TOKYO ELETECH CORPORATION. Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo +81-3-3820-7112 Electronics Dept. Osaka +81-6-6244-6672 Electronics 2nd Dept.
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DEVELOPMENT TOOLS
B.5.2 When using in-circuit emulator IE-78001-R-A
IE-78001-R-A In-circuit emulator This is an in-circuit emulator for debugging the hardware and software when an application system using the 78K/0 Series is developed. It supports an integrated debugger (ID78K0). This emulator is used with an emulation probe and interface adapter for connecting a host machine. This adapter is necessary when a PC-9800 series PC (except notebook type) is used as the host machine for the IE-78001-R-A (C bus compatible). This adapter is necessary when an IBM PC/AT or compatible machine is used as the host machine for the IE-78001-R-A (ISA bus compatible). This board is used with an in-circuit emulator to emulate device-specific peripheral hardware. This probe is for an 80-pin plastic QFP (GC-8BT type) and connects an in-circuit emulator and the target system. EV-9200GC-80 Conversion socket (See Figure B-2) EP-78054GK-R Emulation probe TGK-080SDW Conversion adapter (See Figure B-3) This conversion socket connects the board of the target system created to mount an 80-pin plastic QFP (GC-8BT type) and EP-78230GC-R.
IE-70000-98-IF-C Interface adapter IE-70000-PC-IF-C Interface adapter IE-780308-R-EM Emulation board EP-78230GC-R Emulation probe
This probe is for an 80-pin plastic TQFP (GK-9EU type) and connects an in-circuit emulator and the target system. This conversion adapter connects the board of the target system created to mount an 80-pin plastic TQFP (GK-9EU type) and EP-78054GK-R.
Remarks 1. TGK-080SDW is a product of TOKYO ELETECH CORPORATION. Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo +81-3-3820-7112 Electronics Dept. Osaka +81-6-6244-6672 Electronics 2nd Dept. 2. The EV-9200GC-80 is sold in sets of five units. 3. The TGK-080SDW is sold in single units.
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APPENDIX B
DEVELOPMENT TOOLS
B.6 Debugging Tools (Software)
SM78K0 System simulator This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with a device file (DF780058) (sold separately). Part Number: SxxxxSM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulators IE-78K0-NS and IE-78K0-NS-A) ID78K0 Integrated debugger (supporting in-circuit emulator IE-78001-R-A) This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with a device file (sold separately). Part Number: SxxxxID78K0-NS SxxxxID78K0
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSM78K0 SxxxxID78K0-NS SxxxxID78K0
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD
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DEVELOPMENT TOOLS
B.7 Embedded Software
RX78K0 Real-time OS The RX78K0 is a real-time OS conforming to the ITRON specifications. A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780058) (both sold separately). The real-time OS is a DOS-based application. It should be used in the DOS prompt when using in Windows. Part number: SxxxxRX78013-
Caution When purchasing the RX78K0, fill in the purchase application form in advance and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxRX78013-
001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Source program for mass-produced object
xxxx AA13 AB13 BB13
Host Machine PC-9800 series IBM PC/AT and compatibles
OS Windows (Japanese version) Windows (Japanese version) Windows (English version)
Supply Medium 3.5-inch 2HD FD
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DEVELOPMENT TOOLS
B.8 System-Upgrade Method from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
If you already have a former in-circuit emulator for 78K/0 Series microcontrollers (IE-78000-R or IE-78000-R-A), that in-circuit emulator can operate as an equivalent to the IE-78001-R-A by replacing its internal break board with the IE-78001-R-BK. Table B-1. System-Upgrade Method from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
In-Circuit Emulator Owned IE-78000-R IE-78000-R-A In-Circuit Emulator Cabinet System-UpNote Required Not required Board to Be Purchased IE-78001-R-BK
Note For upgrading a cabinet, send your in-circuit emulator to NEC Electronics.
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DEVELOPMENT TOOLS
B.9 Drawing and Footprint for Conversion Socket (EV-9200GC-80)
Figure B-2. EV-9200GC-80 Drawing (For Reference Only)
A E B F M N O
D
C
R S J
K
EV-9200GC-80
1
No.1 pin index
P
G H I EV-9200GC-80-G0 ITEM A B C D E F G H I J K L M O N P Q R S MILLIMETERS 18.0 14.4 14.4 18.0 4-C 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 INCHES 0.709 0.567 0.567 0.709 4-C 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
2.3 1.5
Q
0.091 0.059
L
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DEVELOPMENT TOOLS
Figure B-3. EV-9200GC-80 Footprint (For Reference Only)
Based on EV-9200GC-80 (2) Pad drawing (in mm)
G
J K
D E F H
L
C B A EV-9200GC-80-P1E ITEM A B C D E F G H I J K L Caution MILLIMETERS 19.7 15.0 INCHES 0.776 0.591
0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486+0.003 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026+0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 0.591 0.776 0.236+0.003 -0.002 0.236+0.003 -0.002 0.014+0.001 -0.001
2.36 0.03 2.3 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
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APPENDIX B
DEVELOPMENT TOOLS
B.10 Drawing of Conversion Adapter (TGK-080SDW, TGC-080SBP)
Figure B-4. TGK-080SDW Drawing (For Reference Only) (Unit: mm)
TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm)
A B C D R Q Q Q P S O O O N I JJJ K L L LM gv k j i h p l n m
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 18.0 11.77 0.5x19=9.5 0.5 0.5x19=9.5 11.77 18.0 0.5 1.58 1.2 7.64 1.2 1.58 1.58 1.2 7.64 1.2 1.58 INCHES 0.709 0.463 0.020x0.748=0.374 0.020 0.020x0.748=0.374 0.463 0.709 0.020 0.062 0.047 0.301 0.047 0.062 0.062 0.047 0.301 0.047 0.062 ITEM a b c d e f g h i j k l m n o p q r s t u v MILLIMETERS 0.5x19=9.50.10 0.25 INCHES 0.020x0.748=0.3740.004 0.010
T
U V
c
e b a
M2 screw
GFE
H
d
W X Y u r t s q
Z
f
Protrusion : 4 places
o
5.3 5.3 1.3 3.55 0.3
1.850.2 3.5 2.0 3.0 0.25 14.0 1.40.2 1.40.2 h=1.8 1.3 0~5 5.9 0.8 2.4 2.7 3.9
0.209 0.209 0.051 0.140 0.012
0.0730.008 0.138 0.079 0.118 0.010 0.551 0.0550.008 0.0550.008 h=0.071 0.051 0.000~0.197 0.232 0.031 0.094 0.106 0.154 TGK-080SDW-G1E
3.55
C 2.0 12.31 10.17 6.8 8.24 14.8 1.40.2
0.140
C 0.079 0.485 0.400 0.268 0.324 0.583 0.0550.008
note: Product by TOKYO ELETECH CORPORATION.
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DEVELOPMENT TOOLS
Figure B-5. TGC-080SBP Drawing (For Reference Only) (Unit: mm)
Reference diagram: TGC-080SBP (TQPACK080SB+TQSOCKET080SBP) Package dimension (unit: mm)
I C A B J K
W
N R GFED L
S Protrusion height T
V
U M
H Y Z g c f b e d h j i k X m l
O P Q
a
note: Product by TOKYO ELETECH CORPORATION.
;
ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
MILLIMETERS 21.0 0.65x19=12.35 0.65 10.35 12.75 15.15 17.55 14.47 C 2.0 14.95 13.95 13.7 1.15 1.15 12.62 17.52 21.0 5.0 4- 1.3 1.8
INCHES 0.827 0.026x0.748=0.486 0.026 0.407 0.502 0.596 0.691 0.570 C 0.079 0.589 0.549 0.539 0.045 0.045 0.497 0.690 0.827 0.197 4- 0.051 0.071
ITEM a b c d e f g h i j k l m
MILLIMETERS (16.95) 7.35 1.2 1.85 3.5 2.0 6.0 0.25 13.95 1.025 1.025 2.4 2.7
INCHES (0.667) 0.289 0.047 0.073 0.138 0.079 0.236 0.010 0.549 0.040 0.040 0.094 0.106
TGC-080SBP-G0E
5.3
7.7 4-C 1.0
0.209
0.303 4-C 0.039
3.55 0.9 0.3
0.140 0.035 0.012
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DEVELOPMENT TOOLS
B.11 Cautions on Designing Target System
Figures B-6 to B-9 show the conditions when connecting the emulation probe to the conversion socket. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. (1) NP-80GC, NP-80GC-TQ, NP-H80GC-TQ Figure B-6. Distance Between In-Circuit Emulator and Conversion Socket (80GC)
In-circuit emulator IE-78K0-NS or IE-78K0-NS-A Target system Emulation board IE-780308-NS-EM1 155 mmNote
CN6
Emulation probe NP-80GC, NP-80GC-TQ, NP-H80GC-TQ
Conversion socket EV-9200GC-80 or conversion adapter TGC-080SBP
Note When NP-H80GC-TQ is used, the distance is 355 mm. Remark NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TGC-080SBP is a product of TOKYO ELETECH CORPORATION.
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DEVELOPMENT TOOLS
Figure B-7. Connection Condition of Target System (NP-80GC-TQ)
Emulation board IE-780308-NS-EM1
Emulation probe NP-80GC-TQ
23 mm
Conversion socket TGC-080SBP
11 mm
40 mm
34 mm
Target system
Remark NP-80GC-TQ is a product of Naito Densei Machida Mfg. Co., Ltd. TGC-080SBP is a product of TOKYO ELETECH CORPORATION.
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DEVELOPMENT TOOLS
(2) NP-80GK, NP-H80GK-TQ Figure B-8. Distance Between In-Circuit Emulator and Conversion Socket (80GK)
In-circuit emulator IE-78K0-NS or IE-78K0-NS-A
Target system Emulation board IE-780308-NS-EM1 155 mmNote
CN6
Emulation probe NP-80GK, NP-H80GK-TQ
Conversion adapter TGK-080SDW
Note When NP-H80GK-TQ is used, the distance is 355 mm. Remark NP-80GK and NP-H80GK-TQ are products of Naito Densei Machida Mfg. Co., Ltd. TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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DEVELOPMENT TOOLS
Figure B-9. Connection Condition of Target System (NP-80GK)
Emulation board IE-780308-NS-EM1
Emulation probe NP-80GK
23 mm
Extension probe TGK-080SDW
11 mm
40 mm
34 mm
Target system
Remark NP-80GK is a product of Naito Densei Machida Mfg. Co., Ltd. TGK-080SDW is a product of TOKYO ELETECH CORPORATION.
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APPENDIX C
REGISTER INDEX
C.1 Register Index (Register Name)
16-bit timer mode control register (TMC0) ........................................................................................................ 171 16-bit timer output control register (TOC0) ....................................................................................................... 174 16-bit timer register (TM0) ................................................................................................................................. 168 8-bit timer mode control register (TMC1) .......................................................................................................... 216 8-bit timer output control register (TOC1) ......................................................................................................... 217 8-bit timer register 1 (TM1) ................................................................................................................................ 213 8-bit timer register 2 (TM2) ................................................................................................................................ 213 [A] A/D conversion result register (ADCR) ............................................................................................................. 256 A/D converter input select register (ADIS) ........................................................................................................ 260 A/D converter mode register (ADM) .................................................................................................................. 258 Asynchronous serial interface mode register (ASIM) ....................................................................................... 433 Asynchronous serial interface status register (ASIS) ....................................................................................... 436 Automatic data transmit/receive address pointer (ADTP) ................................................................................ 385 Automatic data transmit/receive control register (ADTC) ................................................................................ 389 Automatic data transmit/receive interval specification register (ADTI) ............................................................ 390 [B] Baud rate generator control register (BRGC) ................................................................................................... 437 [C] Capture/compare control register 0 (CRC0) ..................................................................................................... 173 Capture/compare register 00 (CR00) ................................................................................................................ 167 Capture/compare register 01 (CR01) ................................................................................................................ 168 Compare register 10 (CR10) ............................................................................................................................. 213 Compare register 20 (CR20) ............................................................................................................................. 213 Correction address register 0 (CORAD0) ......................................................................................................... 526 Correction address register 1 (CORAD1) ......................................................................................................... 526 Correction control register (CORCN) ................................................................................................................ 527 [D] D/A conversion value set register 0 (DACS0) .................................................................................................. 277 D/A conversion value set register 1 (DACS1) .................................................................................................. 277 D/A converter mode register (DAM) .................................................................................................................. 278 [E] External interrupt mode register 0 (INTM0) ............................................................................................. 177, 483 External interrupt mode register 1 (INTM1) ............................................................................................. 261, 483 [I] Internal expansion RAM size switching register (IXS) ..................................................................................... 537 Internal memory size switching register (IMS) ........................................................................................ 506, 536
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REGISTER INDEX
Interrupt mask flag register 0H (MK0H) ............................................................................................................ 481 Interrupt mask flag register 0L (MK0L) ............................................................................................................. 481 Interrupt mask flag register 1L (MK1L) .................................................................................................... 481, 499 Interrupt request flag register 0H (IF0H) ........................................................................................................... 480 Interrupt request flag register 0L (IF0L) ............................................................................................................ 480 Interrupt request flag register 1L (IF1L) ................................................................................................... 480, 499 Interrupt timing specification register (SINT) ........................................................................................... 294, 345 [K] Key return mode register (KRM) .............................................................................................................. 143, 500
[M] Memory expansion mode register (MM) .................................................................................................. 142, 505 [O] Oscillation mode select register (OSMS) .......................................................................................................... 151 Oscillation stabilization time select register (OSTS) ........................................................................................ 514 [P] Port 0 (P0) ......................................................................................................................................................... 122 Port 1 (P1) ......................................................................................................................................................... 124 Port 12 (P12) ...................................................................................................................................................... 136 Port 13 (P13) ...................................................................................................................................................... 137 Port 2 (P2) ................................................................................................................................................ 125, 127 Port 3 (P3) ......................................................................................................................................................... 129 Port 4 (P4) ......................................................................................................................................................... 130 Port 5 (P5) ......................................................................................................................................................... 131 Port 6 (P6) ......................................................................................................................................................... 132 Port 7 (P7) ......................................................................................................................................................... 134 Port mode register 0 (PM0) ............................................................................................................................... 138 Port mode register 1 (PM1) ............................................................................................................................... 138 Port mode register 12 (PM12) .................................................................................................................. 138, 472 Port mode register 13 (PM13) ........................................................................................................................... 138 Port mode register 2 (PM2) ............................................................................................................................... 138 Port mode register 3 (PM3) ............................................................................................. 138, 176, 218, 249, 253 Port mode register 5 (PM5) ............................................................................................................................... 138 Port mode register 6 (PM6) ............................................................................................................................... 138 Port mode register 7 (PM7) ............................................................................................................................... 138 Priority specify flag register 0H (PR0H) ............................................................................................................ 482 Priority specify flag register 0L (PR0L) ............................................................................................................. 482 Priority specify flag register 1L (PR1L) ............................................................................................................. 482 Processor clock control register (PCC) ............................................................................................................. 148 Program status word (PSW) ....................................................................................................................... 96, 487 Pull-up resistor option register H (PUOH) ........................................................................................................ 141 Pull-up resistor option register L (PUOL) .......................................................................................................... 141
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REGISTER INDEX
[R] Real-time output buffer register H (RTBH) ....................................................................................................... 471 Real-time output buffer register L (RTBL) ........................................................................................................ 471 Real-time output port control register (RTPC) .................................................................................................. 473 Real-time output port mode register (RTPM) ................................................................................................... 472 Receive buffer register (RXB) ........................................................................................................................... 431 Receive shift register (RXS) .............................................................................................................................. 431 [S] Sampling clock select register (SCS) ....................................................................................................... 178, 485 Serial bus interface control register (SBIC) ............................................................................................. 293, 343 Serial I/O shift register 0 (SIO0) ............................................................................................................... 286, 338 Serial I/O shift register 1 (SIO1) ........................................................................................................................ 385 Serial interface pin select register (SIPS) ......................................................................................................... 441 Serial operating mode register 0 (CSIM0) ............................................................................................... 290, 342 Serial operating mode register 1 (CSIM1) ........................................................................................................ 388 Serial operating mode register 2 (CSIM2) ........................................................................................................ 432 Slave address register (SVA) ................................................................................................................... 286, 338 [T] Timer clock select register 0 (TCL0) ........................................................................................................ 169, 247 Timer clock select register 1 (TCL1) ................................................................................................................. 214 Timer clock select register 2 (TCL2) ................................................................................................ 233, 241, 251 Timer clock select register 3 (TCL3) ................................................................................................ 288, 340, 386 Transmit shift register (TXS) ............................................................................................................................. 431 [W] Watch timer mode control register (TMC2) ...................................................................................................... 236 Watchdog timer mode register (WDTM) ........................................................................................................... 243
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APPENDIX C
REGISTER INDEX
C.2 Register Index (Symbol)
[A] ADCR: ADIS: ADM: ADTC: ADTI: ADTP: ASIM: ASIS: [B] BRGC: [C] CORAD0: Correction address register 0 ......................................................................................................... 526 CORAD1: Correction address register 1 ......................................................................................................... 526 CORCN: CR00: CR01: CR10: CR20: CRC0: CSIM0: CSIM1: CSIM2: [D] DACS0: DACS1: DAM: [I] IF0H: IF0L: IF1L: IMS: INTM0: INTM1: IXS: [K] KRM: [M] MK0H: MK0L: Interrupt mask flag register 0H ....................................................................................................... 481 Interrupt mask flag register 0L ....................................................................................................... 481 Key return mode register ....................................................................................................... 143, 500 Interrupt request flag register 0H ................................................................................................... 480 Interrupt request flag register 0L .................................................................................................... 480 Interrupt request flag register 1L ........................................................................................... 480, 499 Internal memory size switching register ............................................................................... 506, 536 External interrupt mode register 0 ........................................................................................ 177, 483 External interrupt mode register 1 ........................................................................................ 261, 483 Internal expansion RAM size switching register ............................................................................ 537 D/A conversion value set register 0 ............................................................................................... 277 D/A conversion value set register 1 ............................................................................................... 277 D/A converter mode register .......................................................................................................... 278 Correction control register .............................................................................................................. 527 Capture/compare register 00 .......................................................................................................... 167 Capture/compare register 01 .......................................................................................................... 168 Compare register 10 ....................................................................................................................... 213 Compare register 20 ....................................................................................................................... 213 Capture/compare control register 0 ............................................................................................... 173 Serial operating mode register 0 ........................................................................................... 290, 342 Serial operating mode register 1 .................................................................................................... 388 Serial operating mode register 2 .................................................................................................... 432 Baud rate generator control register .............................................................................................. 437 A/D conversion result register ........................................................................................................ 256 A/D converter input select register ................................................................................................. 260 A/D converter mode register .......................................................................................................... 258 Automatic data transmit/receive control register ........................................................................... 389 Automatic data transmit/receive interval specification register .................................................... 390 Automatic data transmit/receive address pointer .......................................................................... 385 Asynchronous serial interface mode register ................................................................................ 433 Asynchronous serial interface status register ............................................................................... 436
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APPENDIX C
REGISTER INDEX
MK1L: MM: [O] OSMS: OSTS: [P] P0: P1: P12: P13: P2: P3: P4: P5: P6: P7: PCC: PM0: PM1: PM12: PM13: PM2: PM3: PM5: PM6: PM7: PR0H: PR0L: PR1L: PSW: PUOH: PUOL: [R] RTBH: RTBL: RTPC: RTPM: RXB: RXS: [S] SBIC: SCS: SFR: SINT:
Interrupt mask flag register 1L .............................................................................................. 481, 499 Memory expansion mode register ......................................................................................... 142, 505
Oscillation mode selection register ................................................................................................ 151 Oscillation stabilization time select register ................................................................................... 514
Port 0 ............................................................................................................................................... 122 Port 1 ............................................................................................................................................... 124 Port 12 ............................................................................................................................................. 136 Port 13 ............................................................................................................................................. 137 Port 2 ...................................................................................................................................... 125, 127 Port 3 ............................................................................................................................................... 129 Port 4 ............................................................................................................................................... 130 Port 5 ............................................................................................................................................... 131 Port 6 ............................................................................................................................................... 132 Port 7 ............................................................................................................................................... 134 Processor clock control register ..................................................................................................... 148 Port mode register 0 ....................................................................................................................... 138 Port mode register 1 ....................................................................................................................... 138 Port mode register 12 ............................................................................................................ 138, 472 Port mode register 13 ..................................................................................................................... 138 Port mode register 2 ....................................................................................................................... 138 Port mode register 3 ..................................................................................... 138, 176, 218, 249, 253 Port mode register 5 ....................................................................................................................... 138 Port mode register 6 ....................................................................................................................... 138 Port mode register 7 ....................................................................................................................... 138 Priority specification flag register 0H ............................................................................................. 482 Priority specification flag register 0L .............................................................................................. 482 Priority specification flag register 1L .............................................................................................. 482 Program status word ................................................................................................................ 96, 487 Pull-up resistor option register H ................................................................................................... 141 Pull-up resistor option register L .................................................................................................... 141
Real-time output buffer register H .................................................................................................. 471 Real-time output buffer register L .................................................................................................. 471 Real-time output port control register ............................................................................................ 473 Real-time output port mode register .............................................................................................. 472 Receive buffer register .................................................................................................................... 431 Receive shift register ...................................................................................................................... 431
Serial bus interface control register ...................................................................................... 293, 343 Sampling clock select register ............................................................................................... 178, 485 Special-function register ................................................................................................................. 115 Interrupt timing specification register .................................................................................... 294, 345
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APPENDIX C
REGISTER INDEX
SIO0: SIO1: SIPS: SVA: [T] TCL0: TCL1: TCL2: TCL3: TM0: TM1: TM2: TMC0: TMC1: TMC2: TOC0: TOC1: TXS: [W] WDTM:
Serial I/O shift register 0 ........................................................................................................ 286, 338 Serial I/O shift register 1 ................................................................................................................. 385 Serial interface pin select register .................................................................................................. 441 Slave address register ........................................................................................................... 286, 338
Timer clock select register 0 ................................................................................................. 169, 247 Timer clock select register 1 .......................................................................................................... 214 Timer clock select register 2 ......................................................................................... 233, 241, 251 Timer clock select register 3 ......................................................................................... 288, 340, 386 16-bit timer register ......................................................................................................................... 168 8-bit timer register 1 ........................................................................................................................ 213 8-bit timer register 2 ........................................................................................................................ 213 16-bit timer mode control register .................................................................................................. 171 8-bit timer mode control register .................................................................................................... 216 Watch timer mode control register ................................................................................................. 236 16-bit timer output control register ................................................................................................. 174 8-bit timer output control register ................................................................................................... 217 Transmit shift register ..................................................................................................................... 431
Watchdog timer mode register ....................................................................................................... 243
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APPENDIX D
REVISION HISTORY
The revision history of this edition is listed in the table below. "Chapter" indicates the chapter of the previous edition where the revision was made.
Edition 2nd edition Revisions Change of following block diagrams of ports: Figures 6-5 and 6-7 P20, P21, and P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block Diagram, Figure 6-9 P30 to P37 Block Diagram, and Figure 6-16 P71 and P72 Block Diagram Addition of Table 7-2 Relationships between CPU Clock and Minimum Instruction Execution Time Addition of Figures 9-10 and 9-13 Square Wave Output Operation Timing Addition of (7) Conversion result immediately after A/D converter start to 14.5 How to Read the A/D Converter Characteristics Table Correction of Note on BSYE in Figure 16-5 Serial Bus Interface Control Register Format Addition of Caution to 16.4.3 (2) (a) Bus release signal (REL) and (b) Command signal (CMD) Addition of (3) MSB/LSB switching as the start bit to 18.4.2 3-wire serial I/O mode operation Change of 18.4.3 (3) (d) Busy control option, (e) Busy & strobe control option, and (f) Bit slippage detection function in old edition to (4) Synchronization control, and improvement of explanation Correction of Figure 19-11 Receive Error Timing Addition of (3) MSB/LSB switching as the start bit to 19.4.3 3-wire serial I/O mode Addition of 19.4.4 Restrictions in UART mode Addition of Note to 26.1 Memory Size Switching Register 26.3 Flash Memory Programming Change of product name of flash programmer from Flashpro to Flashpro II Addition of APPENDIX A DIFFERENCES AMONG PD78054, 78058F, AND 780058 SUBSERIES Total revision: Support of in-circuit emulators IE-78K0-NS and IE-78001-R-A Total revision: Deletion of fuzzy inference development support system APPENDIX C EMBEDDED SOFTWARE APPENDIX A DIFFERENCES AMONG CHAPTER 26 PD78F0058, 78F0058Y CHAPTER 19 SERIAL INTERFACE CHANNEL 2 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (PD780058 Subseries) CHAPTER 14 A/D CONVERTER CHAPTER 9 8-BIT TIMER/EVENT COUNTER CHAPTER 7 CLOCK GENERATOR Chapter CHAPTER 6 PORT FUNCTIONS
PD78054, 78058F, AND 780058 SUBSERIES
APPENDIX B DEVELOPMENT TOOLS
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APPENDIX D
REVISION HISTORY
Edition 3rd edition Deletion of following product * PD780058Y
Revisions
Chapter Throughout
Addition of following products * PD780058B, 780058BY, 780053(A), 780053Y(A), 780054(A), 780054Y(A), 780055(A), 780055Y(A), 780056(A), 780056Y(A), 780058B(A), 780058BY(A) Deletion of following packages * 80-pin plastic QFP (GC-3B9 type) * 80-pin plastic TQFP (GK-BE9 type) Addition of following package * 80-pin plastic TQFP (GK-9EU type) 1.1 Features, 1.7 Outline of Functions * Change of operating voltage range of A/D and D/A converters of CHAPTER 1 OUTLINE (PD780058 SUBSERIES)
PD780058 and 78F0058 * Change of supply voltage of PD78F0058
Addition of 1.9 Differences Between Standard Model and (A) Model 2.1 Features, 2.7 Outline of Functions * Change of operating voltage range of A/D and D/A converters of PD78F0058Y * Change of supply voltage of PD78F0058Y Addition of 2.9 Differences Between Standard Model and (A) Model Change of processing when A/D converter is not used in 3.2.11 AVREF0 Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and VPP pins in Table 3-1 Pin I/O Circuit Types Change of processing when A/D converter is not used in 4.2.11 AVREF0 Change of recommended connection of unused pins and connection of P60 to P63, AVREF1, and VPP pins in Table 4-1 Pin I/O Circuit Types Modification of Note 2 in 6.2.8 Port 6 Addition of note on feedback resistor to Figure 7-3 Format of Processor Clock Control Register Addition of Table 8-5 INTP1/TI01 Pin Valid Edge and CR00 Capture Trigger Valid Edge Addition of Table 8-6 INTP0/TI00 Pin Valid Edge and CR01 Capture Trigger Valid Edge Correction of note on valid edge of INTP0/TI00/P00 and INTP1/TI01/P01 pin in Figure 8-8 Format of External Interrupt Mode Register 0 Addition of Figure 8-17 Configuration of PPG Output Addition of Figure 8-18 PPG Output Operation Timing 8.5 16-Bit Timer/Event Counter Operating Cautions Addition of description on TI01/P01/INTP1 to (5) Valid edge setting Addition of (c) One-shot pulse output function to (6) Re-trigger of one-shot pulse Addition of (8) Conflict operation Addition of (9) Timer operation Addition of (10) Capture operation Addition of (11) Compare operation Addition of (12) Edge detection Modification of note on changing count clock in Figure 10-2 Format of Timer Clock Select Register 2 CHAPTER 10 WATCH TIMER CHAPTER 3 PIN FUNCTIONS (PD780058 SUBSERIES) CHAPTER 2 OUTLINE (PD780058Y SUBSERIES)
CHAPTER 4 PIN FUNCTIONS (PD780058Y SUBSERIES)
CHAPTER 6 PORT FUNCTIONS CHAPTER 7 CLOCK GENERATOR CHAPTER 8 16-BIT TIMER/EVENT COUNTER
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APPENDIX D
REVISION HISTORY
Edition 3rd edition
Revisions Modification of note on changing count clock in Figure 11-2 Format of Timer Clock Select Register 2 Addition of note on rewriting TCL2 in Figure 13-2 Format of Timer Clock Select Register 2 Modification of Figure 14-5 A/D Converter Basic Operation Addition of Table 14-2 A/D Conversion Sampling Time and A/D Converter Start Delay Time Addition of 14.5 How to Read A/D Converter Characteristics Table 14.6 A/D Converter Cautions Change of description in (1) Power consumption in standby mode Addition of (3) Conflicting operations Addition of (6) Input impedance of ANI0 to ANI7 pins Addition of (10) Timing at which A/D conversion result is undefined Addition of (11) Notes on board design Addition of (12) AVREF0 pin Addition of (13) Internal equivalent circuit of ANI0 to ANI7 pins and permissible signal source impedance Addition of description of processing when D/A converter is not used in 15.5 D/A Converter Cautions (3) AVREF1 pin Addition of 17.4.7 Restrictions in I2C bus mode 2
Chapter CHAPTER 11 WATCHDOG TIMER CHAPTER 13 BUZZER OUTPUT CONTROLLER CHAPTER 14 A/D CONVERTER
CHAPTER 15 D/A CONVERTER CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (PD780058Y SUBSERIES) CHAPTER 19 SERIAL INTERFACE CHANNEL 2 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
Addition of 19.4.5 Restrictions in UART mode 2
Addition of Caution when interrupt is acknowledged to Figure 21-2 Format of Interrupt Request Flag Register Addition of description on TI01/P01/INTP1 pin to Figure 21-5 Format of External Interrupt Mode Register 0 Addition of Caution to 25.1 ROM Correction Function Modification of Table 26-1 Differences Between PD78F0058, 78F0058Y and Mask ROM Versions Total revision of description on flash memory programming as 26.3 Flash Memory Characteristics Addition of CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION)
CHAPTER 25 ROM CORRECTION CHAPTER 26 PD78F0058, 78F0058Y
CHAPTER 28 ELECTRICAL SPECIFICATIONS (MASK ROM VERSION) CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION) CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V)) CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES) CHAPTER 32 PACKAGE DRAWINGS
Addition of CHAPTER 29 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION)
Addition of CHAPTER 30 ELECTRICAL SPECIFICATIONS (FLASH MEMORY VERSION (VDD = 2.2 V))
Addition of CHAPTER 31 CHARACTERISTICS CURVES (REFERENCE VALUES)
Addition of CHAPTER 32 PACKAGE DRAWINGS
User's Manual U12013EJ3V2UD
693
APPENDIX D
REVISION HISTORY
Edition 3rd edition
Revisions Addition of CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS Correction of APPENDIX A DIFFERENCES BETWEEN PD78054, 78058F, AND 780058
Chapter CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS APPENDIX A DIFFERENCES BETWEEN PD78054, 78058F, AND 780058 SUBSERIES APPENDIX B DEVELOPMENT TOOLS
Total revision of APPENDIX B DEVELOPMENT TOOLS Transfer of description of embedded software to APPENDIX B DEVELOPMENT TOOLS
694
User's Manual U12013EJ3V2UD

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